Architecture, method(s) and circuitry for low power memories

Static information storage and retrieval – Addressing – Plural blocks or banks

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365 63, 3652335, G11C 800

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active

061634956

ABSTRACT:
A circuit comprising a first and second bitline, a plurality of groups of memory cells and a control circuit. The first and second bitlines may each be configured to read and write to one or more of the plurality of groups of memory cells. Each of the plurality of bitline pairs may be interdigitated. The control circuit may be configured to select an active group of said plurality of groups in response to one or more control signals. The control circuit may be implemented within the groups of memory cells.

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