Architecture incorporating configurable controller for...

Details Architecture incorporating configurable controller for... Architecture incorporating configurable controller for...

2011-05-31

2011-05-31

Connolly, Mark (Department: 2115)

Electrical computers and digital processing systems: support

Computer power control

C713S002000, C713S320000, C713S324000, C712S228000

Reexamination Certificate

active

07953994

ABSTRACT:
The present invention provides a method and system for controlling leakage power consumption at a System on Chip (SoC) level during a normal run or a boot-up mode. The leakage power reduction is achieved by incorporating a central programmable controller in the SoC architecture and test structures of idle SoC peripherals to place them into an Absolute Minimum Power consumption state with respect to static and dynamic power.

REFERENCES:
patent: 5303171 (1994-04-01), Belt et al.
patent: 5339437 (1994-08-01), Yuen
patent: 2003/0226048 (2003-12-01), Nguyen et al.
patent: 2008/0133898 (2008-06-01), Newburn et al.
patent: 2009/0089562 (2009-04-01), Schuchman et al.

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