Computer graphics processing and selective visual display system – Computer graphics display memory system – Plural storage devices
Reexamination Certificate
2000-11-03
2004-03-09
Bella, Matthew C. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Plural storage devices
C345S215000, C345S215000, C345S215000, C345S215000, C348S716000
Reexamination Certificate
active
06704020
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of video decompressing and, more particularly, to an architecture for video decompressor to efficiently access synchronous memory.
2. Description of Related Art
With the progress of the digital electronic technique, the use of the digitized video data has greatly increased the convenience in enjoying a video article. However, the size of the digitized video data is always so tremendous, and thus, the data must be compressed to reduce its size for transmission or storage. For those skilled in the art, there are several well-known practical video compressing standards, for example, the JPEG, MPEG1, MPEG2, MPEG4 and H.26X.
It is known that a similarity is generally existed between the front and end portions of the video data, so that there is a redundancy in the video data. Therefore, some of the compressing standards utilize an algorithm to remove such a time redundancy, so as to compress the video data. For example, the MPEG system utilizes a motion compensation method to achieve the purpose of data compressing. In a typical MPEG2 application, if the video data to be decompressed is of NTSC format, the size of data required to be processed is 720×480×1.5×(17×17)/(16×16) bits. Further for processing the data for reading and displaying the bitstream, and system application, the total data bandwidth required is much more than 100M bytes/sec. However, the most economic amount of memory used in the MPEG2 MP@ML standard is 16M bits. Therefore, neither the fast page mode DRAM (Dynamic Random Access Memory) nor the EDO (Extended Data Out) DRAM can meet such a memory requirement.
Currently, the synchronous DRAM (hereinafter abbreviated as SRAM) is getting popular, which provides a larger bandwidth; for example, the 16-bit SDRAM has a bandwidth more than 100 words/sec. In use of the SDRAM, the best data access performance is achieved by alternately accessing the A-bank and B-bank of the SDRAM. Otherwise, the memory banks of the SDRAM must be pre-charged, which results in a waste of more than six operating cycles. Therefore, it is desirable to fully utilize the bandwidth of the SDRAM to promote the memory access efficiency for a video decompressor.
SUMMARY OF THE INVENTION
The object of the present invention is to provide an architecture for video decompressor to efficiently access synchronously memory, which always performs memory operations by alternately accessing the A-bank and B-bank, so as to effectively utilize the bandwidth of the SDRAM thereby significantly increasing the memory access efficiency.
According to one aspect, the present invention which achieves the object relates to an architecture for video decompressor to efficiently access synchronous memory, comprising a synchronous memory device having an A-bank and B-bank for being stored with image data, and a memory controller for controlling data access to the synchronous memory to perform motion compensation and display. The image data has a plurality of scan lines and every four scan lines are grouped for being periodically arranged in the synchronous memory in such a manner that the A-bank is sequentially stored with (4N+0)-th and (4N+1)-th scan lines, and the B-bank is sequentially stored with the (4N+2)-th and (4N+3)-th scan lines, where N is a non-negative integer.
According to another aspect, the present invention which achieves the object relates to an architecture for video decompressor to efficiently access synchronous memory, comprising a synchronous memory device having an A-bank and B-bank for being stored with image data, and a memory controller for controlling data access to the synchronous memory to perform motion compensation and display. The image data has a plurality of luminance scan lines and every eight scan lines are grouped for being periodically arranged in the synchronous memory in such a manner that the A-bank is sequentially stored with (8N+0)-th, (8N+1)-th, (8N+6)-th and (8N+7)-th scan lines, and the B-bank is sequentially stored with the (8N+2)-th, (8N+3)-th, (8N+4)-th and (8N+5)-th scan lines, where N is a non-negative integer. The image data has a plurality of chrominance scan lines and every eight scan lines are grouped for being periodically arranged in such a manner that the A-bank is sequentially stored with (8N+1)-th, (8N+2)-th, (8N+5)-th and (8N+6)-th scan lines, and the B-bank is sequentially stored with (8N+0)-th, (8N+3)-th, (8N+4)-th and (8N+7)-th scan lines, where N is a non-negative integer.
According to a further aspect, the present invention which achieves the object relates to an architecture for video decompressor to efficiently access synchronous memory, comprising a synchronous memory device having an A-bank and B-bank for being stored with image data, and a memory controller for controlling data access to the synchronous memory to perform motion compensation and display. The image data has a plurality of luminance scan lines and every eight scan lines are grouped for being periodically arranged in the synchronous memory in such a manner that the A-bank is sequentially stored with (8N+0)-th, (8N+2)-th, (8N+5)-th and (8N+7)-th scan lines, and the B-bank is sequentially stored with the (8N+1)-th, (8N+3)-th, (8N+4)-th and (8N+6)-th scan lines, where N is a non-negative integer. The image data has a plurality of chrominance scan lines and every eight scan lines are grouped for being periodically arranged in such a manner that the A-bank is sequentially stored with (8N+1)-th, (8N+2)-th, (8N+5)-th and (8N+6)-th scan lines, and the B-bank is sequentially stored with (8N+0)-th, (8N+3)-th, (8N+4)-th and (8N+7)-th scan lines, where N is a non-negative integer.
Other objects, advantages, and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5170468 (1992-12-01), Shah et al.
patent: 6088047 (2000-07-01), Bose et al.
patent: 6411334 (2002-06-01), Yeh et al.
patent: 6493005 (2002-12-01), Wu
Chen Wen-Kuan
Liao Jen-Yi
Bacon & Thomas PLLC
Bella Matthew C.
Quillen Allen E
Sunplus Technology Co. Ltd.
LandOfFree
Architecture for video compressor to efficiently address... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Architecture for video compressor to efficiently address..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Architecture for video compressor to efficiently address... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3246033