Architecture for the isochronous transfer of information within

Details Architecture for the isochronous transfer of information within Architecture for the isochronous transfer of information within

1998-07-06

2000-09-12

De Cady, Albert

Electrical computers and digital processing systems: support

Clock control of data processing system, component, or data...

710 21, 710 61, 712225, G06F 104

Patent

active

061192430

ABSTRACT:
An architecture for the isochronous transfer of information within a computer system in which a first isochronous stream of information is transferred, and asynchronous information is transferred independently from the transfer of the first stream. A translation is performed between the first stream and a second isochronous stream of information, and the second stream transfers information at a rate substantially the same as the rate at which the first stream transfers information. The second stream and the asynchronous information are concurrently transferred. In another embodiment of the present invention, a first isochronous stream of information is transferred, and the first stream is divided into a plurality of first service periods. Each first service period has a first duration and contains a first amount of information. A second isochronous stream of information is transferred independently from the transfer of the first stream. The second stream is divided into a plurality of second service periods, and each second service period has a second duration and contains a second amount of information. A translation is performed between (1) the first and second streams and (2) a third isochronous stream of information. The third stream is divided into a plurality of third service periods, and each third service period has a third duration and contains a third amount of information.

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