Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1998-06-16
2002-03-12
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C326S046000
Reexamination Certificate
active
06356974
ABSTRACT:
TECHNICAL FIELD
The present invention relates to flash memory systems, and more specifically, to an architecture for a state machine used to control the internal data processing operations of a flash memory. The state machine uses a central controller to control the execution of the sub-operations common to the data processing operations. The state machine of the present invention has fewer logic gates and is more compact than the set of state machines currently used for such purposes.
BACKGROUND OF THE INVENTION
In early integrated circuit memory systems, the detailed operation of the memory system was controlled directly by a processor unit which utilized the memory. Since the operation of many memory systems requires a substantial amount of processor overhead, many such systems now include an internal state machine for controlling the detailed operation of the memory system. The internal state machine controls the primary operations of the memory system, including the reading, programming and erasing operations performed on the memory elements. Each of these primary operations is comprised of a large number of sub-operations which are necessary to carry out the primary operations, with these sub-operations also being controlled by the primary state machine or in some cases by a secondary one.
FIG. 1
is a functional block diagram of a conventional flash memory system
100
. The core of memory system
100
is an array
112
of flash memory cells. The individual cells in array
112
are arranged in rows and columns, with there being, for example, a total of 256 K eight bit words in array
112
. The individual memory cells (not shown) are accessed by using an eighteen bit address A
0
-A
17
, which is input by means of address pins
113
. Nine of the eighteen address bits are used by X decoder
114
to select the row of array
112
in which a desired memory cell is located and the remaining nine bits are used by Y decoder
116
to select the appropriate column of array
112
in which the desired cell is located. Sense amplifiers
119
are used to read the data contained in a memory cell during a read operation or a data verification step in which the state of a cell is determined after a programming, pre-programming, or erase operation. This circuitry can be combined with the data compare and verify circuits used to compare the state of a cell to a desired state or to input data.
Memory system
100
contains an internal state machine (ISM)
120
which controls the data processing operations and sub-operations performed on memory array
112
. These include the steps necessary for carrying out programming, reading and erasing operations on the memory cells of array
112
. In addition, internal state machine
120
controls such operations as reading or clearing status register
126
, identifying memory system
100
in response to an identification command, and suspending an erase operation. State machine
120
functions to reduce the overhead required of an external processor (not depicted) typically used in association with memory system
100
.
For example, if memory cell array
112
is to be erased (typically, all or large blocks of cells are erased at the same time), the external processor causes the output enable pin {overscore (OE)} to be inactive (high), and the chip enable {overscore (CE)} and write enable {overscore (WE)} pins to be active (low). The processor then issues an 8 bit command 20H (0010 0000) on data I/O pins
115
(DQ
0
-DQ
7
), typically called an Erase Setup command. This is followed by the issuance of a second eight bit command DOH (1101 0000), typically called an Erase Confirm command. Two separate commands are used to initiate the erase operation so as to minimize the possibility of inadvertently beginning an erase procedure.
The commands issued on I/O pins
115
are transferred to data input buffer
122
and then to command execution logic unit
124
. Command execution logic unit
124
receives and interprets the commands which instruct state machine
120
to initiate the steps required for erasing array
112
or carrying out another desired operation. Once the desired operation sequence is completed, state machine
120
updates 8 bit status register
126
. The contents of status register
126
is transferred to data output buffer
128
, which makes the contents available on data I/O pins
115
of memory system
100
. Status register
126
permits the external processor to monitor certain aspects of the status of state machine
120
during memory array write and erase operations. The external processor periodically polls data I/O pins
115
to read the contents of status register
126
in order to determine whether an erase sequence (or other operation) has been completed and whether the operation was successful.
FIG. 2
is a state diagram showing the states of an erase state machine during the performance of an erase operation on a memory system such as that shown in FIG.
1
. As indicated by the figure, an erase operation includes pre-program
200
, high voltage (internal) erase
220
, and erase healing (distribution adjustment)
240
stages. As shown in the figure, each of these primary stages in an erase operation is typically implemented in the form of a separate state machine.
The erase operation begins with an erase set-up stage
260
which is initiated by application of the appropriate commands on data I/O pins
115
(DQ
0
-DQ
7
) of
FIG. 1
, and any other appropriate control signals applied on the relevant lines. The function of stage
260
is to set up a node that indicates that the part is being erased. From this state, the state machine either transitions to pre-program state
200
along path
262
, or if instructed to skip that stage, along path
264
. If the state machine transitions to the pre-program stage, pre-program state machine
200
then carries out that operation. This sub-operation programs all the elements in the memory array to a logic 0 value to make sure that the erase process starts from a known cell threshold voltage level. This part of the complete erase operation is used to reduce the possibility of over erasure of some of the memory elements during the later steps. When the pre-program operation has been completed on the memory elements, the erase state machine transitions along path
265
to the next stage, unless the state machine has been instructed to suspend the erase operation. If a problem occurs during the pre-program stage, control is passed out of that stage along path
263
.
When the pre-program operation is complete, or if that operation was skipped, the erase state machine transitions to erase high voltage (internal erase) stage
220
. As noted in
FIG. 2
, this stage is typically implemented in the form of a state machine. In the erase high voltage stage, the memory system performs a block erase operation on all of the cells contained in a block of memory. This has the effect of erasing all of the memory elements to a logic 1 value.
Upon successful completion of the high voltage erase operation, the erase state machine transitions to either the erase healing stage
240
or to the erase clean up stage
270
. If the erase operation was successful and the heal operation has not been performed, the erase state machine transitions along path
266
to healing state machine
240
. In the erase healing operation, the memory cells in the array are corrected (if necessary) for the effects of accidental over-erasure, in which case the threshold voltage of a cell has been driven down to zero or a negative value. When this operation has been completed for the block of memory elements which has been erased, the erase state machine transitions back along path
268
to the erase high voltage state machine
220
. This is because the erase high voltage operation may need to be repeated to further adjust the threshold voltage levels of the memory cells after they have been altered by the healing operation. This cycle can be repeated until the erase high voltage operation and the healing operation have produced a desired rang
Portka Gary J.
Schwegman Lundberg Woessner & Kluth P.A.
Yoo Do Hyun
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