Architecture for programmable on-chip termination

Details Architecture for programmable on-chip termination Architecture for programmable on-chip termination

2002-03-19

2004-11-30

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C326S030000

Reexamination Certificate

active

06826734

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to on-chip termination resistors and more specifically to a programmable on-chip termination resistance.
BACKGROUND OF THE INVENTION
The Low Voltage Differential Swing (LVDS) standard provides a data interface that has a balance I/O buffer driver that sends data by current signaling in a balanced interconnect environment. LVDS is adapted for high-speed transmission of binary data over copper. An advantageous aspect of LVDS is provided due to the response of LVDS receivers to differential voltages, thus LVDS receivers are fairly immune to noise and emit less electromagnetic interference (EMI) than other data transmission standards.
A problem associated with LVDS compliant interfaces is a requirement of a precise line termination resistance. A line termination resistance, fabricated according to various methods, is typically placed in front of a LVDS receiver to maintain signal quality and integrity. LVDS circuits must provide buffers to ensure a signal current of typically 4.0 milliAmperes on a voltage drop across the on-chip resistance from of typically 400 milliVolts. In order to provide a resistor termination to an LVDS transmission line that does not suffer symmetrical signal distortion, an on-chip resistance must be of a chosen value and remain within a desired tolerance. The chosen value for the termination resistor may be required to be between 50 Ohms and 150 Ohms to suit the characteristic impedance of the media with a tolerance of ±10%. However, due to temperature and technology variations, an on-chip resistance may vary as much as 30%. Consequently, a programmable on-chip resistance capable of being set to a desired nominal value and capable of adjusting to accommodate process and temperature variations is desirable.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method and apparatus for producing a programmable on-chip resistance. In an embodiment of the invention, a programmable on-chip resistance may be produced based upon an external resistor and is implemented through an analog scheme. The apparatus and method of the present invention may provide a termination resistance that may be adjustable in real-time. An advantageous aspect of the present invention is the ability to minimize parasitic capacitance as seen by a high-speed driver sending data to differential input ports. In one embodiment of the invention, the termination resistance located on-chip may be implemented through a single transistor with an analog control.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention and together with the general description, serve to explain the principles of the invention.


REFERENCES:
patent: 6414512 (2002-07-01), Moyer
patent: 6418500 (2002-07-01), Gai et al.
patent: 6509765 (2003-01-01), Drost
patent: 6586964 (2003-07-01), Kent et al.
patent: 6710618 (2004-03-01), Murray

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