Architecture for multi-queue storage element

Details Architecture for multi-queue storage element Architecture for multi-queue storage element

1999-09-27

2003-10-28

Sparks, Donald (Department: 2187)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output access regulation

C710S039000, C710S052000, C710S316000, C711S118000

Reexamination Certificate

active

06640267

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to storage elements generally and, more particularly, to a method and/or architecture for a multi-queue storage element.
BACKGROUND OF THE INVENTION
Conventional storage circuits cannot manage multi-queue configuration, status information, queue selection, queue reset operation and/or multicast/broadcast support functions. As the spread (i.e., the number of FIFOs) of conventional storage circuits increases, the write enable signal and the read enable signal require additional circuitry, since they are implemented as point-to-multipoint connections.
A delay queue selection write operation requires a point-to-multipoint data interface. The point-to-multipoint interface requires additional circuitry and, in some cases, may even be impossible as the frequency of operation increases. A delay queue selection operation requires an additional management interface. The management interface further requires additional circuitry and, in some cases, may even be impossible as the frequency of operation increases.
A multi-queue operation requires additional external logic to determine the flag status of each queue that is presented on the pin. For example, if
16
flags are presented on the pins for full and empty flags simultaneously,
32
external flag detection logic circuits would be required. A multi-queue operation implementing token-passing further requires complicated end of packet (EOP) logic communication between chips. Additionally, a point to multi-point (or multi-point to point) operation requires additional logic to avoid bus contention at the read interface.
SUMMARY OF THE INVENTION
The present invention concerns a circuit comprising a memory and a logic circuit. The memory may be configured to read and write data in a plurality of memory queues to/from a write data path and a read data path in response to (i) a first and a second select signal and (ii) a first control signal. The logic circuit may be configured to generate (i) the first and second select signals and (ii) the control signal in response to one or more signals received from a read management path and/or a write management path.
The objects, features and advantages of the present invention include providing a multi-queue storage element that may (i) comprise variable sized queues, (ii) automatically move to a different block in response to an end-of-packet (EOP), (iii) provide flexible flag access and/or (iv) provide a high speed interface.


REFERENCES:
patent: 5692138 (1997-11-01), Fandrich et al.
patent: 5717875 (1998-02-01), Cutlerywala et al.
patent: 5732269 (1998-03-01), Compton et al.
patent: 5802552 (1998-09-01), Fandrich et al.
patent: 5956522 (1999-09-01), Bertone et al.
patent: 6128702 (2000-10-01), Saulsbury et al.

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