Architecture for high-speed magnetic memories

Details Architecture for high-speed magnetic memories Architecture for high-speed magnetic memories

2002-12-13

2004-08-17

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Magnetic thin film

C365S189020, C365S189090

Reexamination Certificate

active

06778431

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to memory circuits, and more particularly relates to techniques for reading and writing magnetic random access memory (MRAM).
BACKGROUND OF THE INVENTION
FIG. 1
illustrates a conventional magnetic tunnel junction (MTJ) device
100
. The MTJ
100
is typically comprised of a stack of two ferromagnetic layers (ML) separated by a tunnel barrier (TL) at a cross-point of two conductors, one of which may be a word line (WL) and the other a bit line (BL). One of the two magnetic layers is often referred to as a free magnetic layer. The magnetic orientation of the free magnetic layer can be changed by the superposition of magnetic fields generated by programming currents I
WL
and I
BL
flowing in the conductors WL and BL, respectively. The other of the two magnetic layers ML is often referred to as a fixed magnetic layer. The programming currents I
WL
and I
BL
cannot change the magnetic orientation of the fixed magnetic layer. The logical state (e.g., a “0” bit or a “1” bit) is generally stored in the MTJ
100
by changing the orientation of the free magnetic layer relative to the fixed magnetic layer. When both magnetic layers have the same orientation, the MTJ
100
typically has a low resistance R
C
associated therewith, as measured between conductors WL and BL. Likewise, the resistance R
C
of the MTJ
100
is generally high when the magnetic layers are oriented in opposite directions with respect to one another.
A conventional MRAM generally includes a plurality of MTJ devices connected in an array configuration. Two examples of conventional MRAM arrays are shown in
FIGS. 2A and 2B
.
FIG. 2A
illustrates a cross-point array, wherein each memory cell comprises a single MTJ device connected at an intersection of a word line (e.g., WL
k−1
, WL
k
, WL
k+1
) and a corresponding bit line (e.g., BL
i−1
, BL
i
, BL
i+1
). The MTJ devices are depicted in the figure as representative resistances (e.g., R
C
).
FIG. 2B
illustrates an alternative memory architecture employing a plurality of memory cells, each cell comprising a selection transistor coupled in series with an MTJ device (i.e., a 1T1MTJ memory cell). The selection transistor is used for accessing the corresponding MTJ device during a read operation. MRAM circuits are discussed in further detail, for example, in the article by W. Reohr et al., entitled “Memories of Tomorrow,”
IEEE Circuits and Devices Mag
., pp. 17-27, Vol. 18, No. 5, September 2002, which is incorporated herein by reference.
In order to apply the programming currents, necessary to write the logical state of a selected memory cell, and read out data from the bit lines in the memory array, a column selector circuit (not shown) is typically required. The column selector circuit generally connects a selected bit line with a programming circuit, which provides the cell programming current during a write operation of the memory cell. The column selector circuit also connects the selected bit line to a sense amplifier (not shown) during a read operation of the selected memory cell in order to sense the programmed logical state of the cell.
A conventional MRAM array generally employs a single current source for supplying one of the two programming currents for selectively writing the memory cells in the MRAM array (e.g., I
BL
or I
WL
in FIG.
1
). Generally, within a magnetic memory array, one word line current is required to aid in the selection of one or more memory cells in the array. One or more bit line currents, for one or more respective memory cells of a one or more bit word, are required for writing the memory cells to a zero or one logical state. As stated above, word lines and bit lines routed throughout the memory array convey the programming and sense currents for writing and reading, respectively, selected memory cells in the array. However, each of these word and bit lines has a distributed capacitance associated therewith which increases as a function of the length of the word or bit line. Since the distances between the programming current source and sense current source to the selected memory cell can be significant, especially in larger memory arrays, the corresponding load capacitance associated with the word or bit lines in the selected signal path may likewise be relatively large. In addition, switching circuitry associated with the read and write paths typically contributes significantly to the overall load capacitance. This load capacitance can adversely impact the speed of the memory device.
There exists a need, therefore, for an improved MRAM architecture which addresses the above-mentioned problems exhibited in a conventional MRAM array.
SUMMARY OF THE INVENTION
The present invention is directed to techniques for improving the speed of accessing memory cells in a magnetic memory circuit during a read and/or write operation. The invention, in at least one aspect, accomplishes this by reducing the load capacitance on the bit lines and/or word lines coupled to the memory cells, due primarily to the presence of large switching circuitry (e.g., switches, multiplexers (MUXs), etc.) operatively connected to the bit lines and word lines for selectively directing a sense current and/or programming current through the bit lines and word lines, respectively.
Since a significantly smaller current is used during the read operation to sense the logical state of one or more memory cells, by segregating the switches into a plurality of separate read switches and write switches used for reading and writing, respectively, the read switches can be made considerably smaller compared to the corresponding write switches. The smaller switches will have a significantly reduced capacitance associated therewith, thereby improving the speed of the read operation. Additionally, the speed of the write operation may be significantly improved by dividing a programming current source, which supplies the programming current for writing the logical state of the memory cells for each datum input along a bit line dimension, into a plurality of current sources, each current source coupled to a group of one or more corresponding write bit switches. Therefore, the load capacitances from the write bit switches can be divided among the plurality of corresponding current sources. In this manner, no one current source experiences the total load capacitance, thus reducing the capacitance on the output of each of the current sources and thereby improving the speed of the write operation.
In accordance with one aspect of the invention, a magnetic memory circuit comprises a plurality of memory cells and a plurality of bit lines coupled to the memory cells for selectively accessing one or more of the memory cells. The memory circuit comprises at least one bit line programming circuit, configurable as a current source for generating a programming current for writing a logical state of at least one memory cell and/or a current sink for returning the programming current, and a first set of switches. The first set of switches are disabled at least during a read operation of the memory cells and at least a portion of the first set of switches are selectively enabled during a write operation of the memory cells. Each switch in the first set of switches is configured to selectively couple the at least one bit line programming circuit to a corresponding one of the bit lines in response to a first control signal. The memory circuit further comprises at least one sense amplifier and a second set of switches. The second set of switches are disabled at least during a write operation of the memory cells and at least a portion of the second set of switches are selectively enabled during a read operation of the memory cells. Each switch in the second set of switches is configured to selectively couple the at least one sense amplifier to a corresponding one of the bit lines in response to a second control signal.
These and other objects, features and advantages of the present invention will become apparent from

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