Static information storage and retrieval – Read/write circuit – Noise suppression
Reexamination Certificate
2000-11-09
2002-05-07
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Noise suppression
C365S185110
Reexamination Certificate
active
06385107
ABSTRACT:
TECHNICAL FIELD
This invention relates to an architecture for handling internal voltages in a non-volatile memory.
Specifically, the invention relates to an architecture for handling internal voltages in a non-volatile memory array which is split into first and second mutually independent banks.
The invention relates, particularly but not exclusively, to an architecture for handling internal voltages in a non-volatile memory of the dual-work flash type having a single-voltage supply, and the description to follow will cover this field of application for simplicity's sake.
BACKGROUND OF THE INVENTION
As is well known, although non-volatile memories have attained read speeds far above those available but few years ago, little has been achieved in the respect of modify speed, i.e., memory cell program and erase speed.
In fact, modify operations obey the physics that governs the working of nonvolatile memory cells.
In particular, an erase operation may take as long as hundreds of milliseconds, during which time a memory cannot fill requests for reading from a microprocessor arranged to control the memory operation.
To obviate this problem of operational speed, a new generation of storage devices has been developed in the form of dual-work flash memory devices. These devices are split internally into two independent banks, wherein one bank can be read while the other bank is being erased.
There exists currently a demand for non-volatile storage devices to operate on a single supply voltage: these are usually referred to as single-voltage devices. Furthermore, the value of the device operating voltage has moved from 5V to 1.8V, thereby creating a need for the voltages used within the storage device during the memory cell modify operations to be generated, handled and regulated by special charge pump circuits.
In particular, standard voltage values for application to the gate terminal of a memory cell during modify operations may be:
10V for programming, and
−9V for erasing.
For dual-work flash memories wherein the memory array is split into two banks independent of each other, handling internally generated voltages for cell modify operations proves to be complicated, since a requisite is that one bank can be modified simultaneously as the other is being read.
SUMMARY OF THE INVENTION
An embodiment of this invention provides a method of handling the internal voltages of a non-volatile memory, having such structural and functional features as to be applicable to dual-work storage devices, specifically single-voltage storage devices.
A concept behind this invention is one of duplicating the charge pump circuits provided to generate the internal voltages needed for the memory to operate, and introducing a control system for the operation of those circuits so as to ensure proper working of the memory as a whole.
The features and advantages of an architecture according to this invention will be apparent from the following description of an embodiment thereof, given by way of example and not of limitation with reference to the accompanying drawings.
An embodiment of the invention is directed to an architecture for handling internal voltages in a non-volatile memory array that is split into first and second mutually independent banks. The architecture includes first and second pluralities of generators for generating at least one of said internal voltages. The pluralities of generators are separate from each other and connected to the first and second banks, respectively, of the nonvolatile memory array. The architecture also includes a control system connected to the pluralities of generators to correctly activate the different generators in different conditions of the memory array operation.
REFERENCES:
patent: 5075890 (1991-12-01), Itoh et al.
patent: 5297096 (1994-03-01), Terada et al.
patent: 5381366 (1995-01-01), Kawauchi et al.
patent: 5754482 (1998-05-01), Su et al.
patent: 5892715 (1999-04-01), Hirata et al.
patent: 6044033 (2000-03-01), Jang
Bartoli Simone
Bedarida Lorenzo
Russo Antonio
Sali Mauro
Iannucci Robert
Jorgenson Lisa K.
Le Vu A.
Phung Anh
Seed IP Law Group PLLC
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