Architecture for circuit connection of a vertical transistor

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S327000, C257S328000, C257S508000, C257S509000

Reexamination Certificate

active

06903411

ABSTRACT:
An architecture for connection between regions in or adjacent a semiconductor layer. According to one embodiment a semiconductor device includes a first layer of semiconductor material and a first field effect transistor having a first source/drain region formed in the first layer. A channel region of the transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. The device includes a second field effect transistor also having a first source/drain region formed in the first layer. A channel region of the second transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. A conductive layer comprising a metal is positioned between the first source/drain region of each transistor to conduct current from one first source/drain region to the other first source/drain region.In another embodiment a first device region, is formed on a semiconductor layer. A second device region, is also formed on the semiconductor layer. A conductor layer comprising metal is positioned adjacent the first and second device regions to effect electrical connection between the first and second device regions. A first field effect transistor gate region is formed over the first device region and the conductor layer and a second field effect transistor gate region is formed over the second device region and the conductor layer.

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Hergenrother, J.M., et al., “The Vertical Replacement-Gate (VRG) MOSFET: A 50-nm Vertical MOSFET With Lithography-Independent Gate Length”, I.E.E.E., 4 pages (Mar., 1999).

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