Architecture for a fast frame store using dynamic RAMS

Details Architecture for a fast frame store using dynamic RAMS Architecture for a fast frame store using dynamic RAMS

1985-10-23

1988-02-16

Harkcom, Gary V.

Static information storage and retrieval

Read/write circuit

Parallel read/write

365222, 365189, 364200, 364518, G11C 1140

Patent

active

047259876

ABSTRACT:
A fast frame store incorporating a memory array having selectable memory banks which include a plurality of relatively slow dynamic RAMs (DRAMs) is disclosed. The frame store has a buffered input and a buffered output to slow the data rate. Data can be read in parallel into a selected memory bank while at the same time other data are being read in parallel out of another selected memory bank. Refresh of DRAMs of an unselected bank occurs simultaneously with the transfer of data to or from the frame store. Several memory banks of the frame store are connected to a single row address select (RAS) line, so that when a selected bank is being addressed for data transfer, the memory location of several other unselected banks are being refreshed.

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IBM Technical Disclosure Bulletin, vol. 17, No. 3 (Aug. 1974).
J. Millman, Microelectronics-Digital and Analog Circuits and Systems, McGraw-Hill Book Company, pp. 286-297.

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