Architecture for a data storage device

Details Architecture for a data storage device Architecture for a data storage device

2007-12-11

2007-12-11

Bataille, Pierre (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

Reexamination Certificate

active

10679030

ABSTRACT:
A data storage device architecture includes a HDA printed circuit board (PCB) including a spindle motor driver, a read/write arm driver, a read channel driver, and a first input/output (I/O) interface that are arranged on the HDA PCB. An application PCB includes at least one of an application specific integrated circuit and a processor that performs application and hard drive control related processing. A buffer stores application and hard drive control related data. A hard drive controller (HDC), a mapping driver, and a second I/O interface are arranged on the application PCB. The second I/O interface communicates with the first I/O interface. The mapping driver is capable of at least one of mapping logical addresses to physical addresses and monitoring a location of a read/write head.

REFERENCES:
patent: 5287459 (1994-02-01), Gniewek
patent: 5745671 (1998-04-01), Hodges
patent: 5751514 (1998-05-01), Hyde et al.
patent: 5991399 (1999-11-01), Graunke et al.
patent: 6418474 (2002-07-01), Morris
patent: 6553471 (2003-04-01), O'Hare et al.
patent: 6725342 (2004-04-01), Coulson
patent: 2002/0178320 (2002-11-01), Wu
patent: 2003/0002198 (2003-01-01), Subrahamanyan et al.
patent: 2004/0111634 (2004-06-01), Ingman et al.
patent: 2005/0005044 (2005-01-01), Liu et al.
“Serial ATA: High Speed Serialized AT Attachment”, Serial ATA Organization, Revision 1.0, Aug. 29, 2001; pp. 1-306.
Supplements to “Serial ATA: High Speed Serialized At Attachment”, Serial ATA Organization, Revison 1.0, Aug. 29, 2001, pp. 1, 2, 3, 4, 5, 7.
Errata to “Serial ATA: High Speed Serialized AT Attachment”, Serial ATA Organization, Revision 1.0, Aug. 29, 2001, pp. 1-50.
Intel; 82801EB I/O Controller Hub 5 (ICH5)/Intel 82801ER I/O Controller Hub 5 R (ICH5R); Document No: 252516-001; Datasheet; Apr. 2003; pp. 1-671.

Affiliated with

Also associated with

Rating

Architecture for a data storage device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Architecture for a data storage device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Architecture for a data storage device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3862058