Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
1999-12-06
2003-09-30
Auve, Glenn A. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
Reexamination Certificate
active
06629185
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to post decoding of memory circuits generally and, more particularly, to a post decode method and/or architecture for memory circuits using an interdigitated array.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, a conventional circuit
10
for post decoding of memory circuits is shown. The circuit
10
comprises a plurality of blocks
12
a
-
12
n
, a global data bus
14
, a multiplexer
16
and an I/O circuit
18
. Each block
12
a
-
12
n
presents a signal to an input
20
a
-
20
n
of the global data bus
14
. The global data bus
14
presents a signal to an input
22
of the multiplexer
16
. The multiplexer
16
presents a signal to the I/O circuit
18
in response to the signal received at the input
22
and a signal POST_DECODE_ADDR received at an input
24
. The I/O circuit
18
presents the signal OUTPUT in response to the signals received from the multiplexer
16
.
The blocks
12
a
-
12
n
comprise an array
26
a
-
26
n
, a multiplexer
28
a
-
28
n
and a sense amplifier
30
a
-
30
n
. The array
26
a
is connected to the multiplexer
28
a
. The multiplexer
28
a
is connected to the sense amplifier
30
a
and will transfer data in response to the array
26
a
. The sense amplifier
30
a
is connected to an input
20
a
of the global data bus
14
and will transfer data in response to the multiplexer
28
a.
Timing diagrams of the circuit
10
are shown in
FIGS. 2
a
,
2
b
and
2
c
. The timing diagrams display the problem of race conditions that occur during operation of the circuit
10
. The timing of the signal POST_ADDR is critical to the operation of the circuit
10
.
FIG. 2
a
defines a simplified timing diagram for a non-atd variant of device
10
. The post decode address input to the multiplexer selects one of two bytes of data from the 16-bit global bus and passes the selected byte to the 8-bit I/O. As an example, a logic low level on post decode address will pass even bits of data, while a logic high level will pass odd bits of data. At some time (i.e., tau) after an address change, the data on the 16-bit global data bus will change to that of the selected address GQ(n). This data then passes through the multiplexer to the I/O. The timing of the post decode address is critical for proper functionality of the device. If the post decode address transitions prior to the global data transition, then the data from address n−1, GQ(n−1)odd, will be momentarily passed to the I/O. This will cause the outputs of the device to “glitch” to the incorrect data. This “glitch” is undesirable and can cause performance degradation and excessive noise. Conversely, if the post decode address transitions after the global data transition (
FIG. 2
b
), then the data from address n is properly passed to the I/O. However, the time difference between the global data transition and the post decode data transition (i.e., phi) has a direct adverse impact on the access time of the device. Phi is directly additive to the Taa, or address access time of the device.
FIG. 2
c
defines a simplified timing diagram for an atd variant of device
10
. This type of device generates an atd pulse as a result of an address transition. This atd pulse is used to equalize the data path of the device. As a result, the global data bus is equalized high (or low) during the pulse duration. By necessity the I/O is forced into a high impedance state by the equalized data path. This allows for time during which the post decode address can transition without passing erroneous data to the I/O. The internal post decode address must be positioned within this equalized state in order to avoid the glitches described for the non-atd device.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a first bus, a second bus, a memory and one or more interconnections. The memory may be connected to the first bus and the second bus and may be configured to transfer data over the first bus and the second bus. The one or more interconnections may be connected between one or more data lines of the first bus and the second bus to control a bit-width of the first and second buses.
The objects, features and advantages of the present invention include providing a method and/or architecture that may (i) transform a memory with an internal bus width of N to a device with an external bus width of N/2
m
using the same base design, (ii) multiplex a single ended data path without inducing unnecessary output data transitions, (iii) have an access time which is not dependent on a post decode address speed, and/or (iv) define post decoding of memories with interdigitated arrays. In one example, the present invention may be used with differential data and a non-interdigitated array.
REFERENCES:
patent: 5274763 (1993-12-01), Banks
patent: 5363494 (1994-11-01), Kudou
patent: 5761456 (1998-06-01), Titus et al.
patent: 6049501 (2000-04-01), Pantelakis et al.
patent: 6101565 (2000-08-01), Nishtala et al.
patent: 6311239 (2001-10-01), Matthews
Ford Keith
Gradinariu Iulian
Mulholland Sean
Silver John
Auve Glenn A.
Cypress Semiconductor Corp.
Maiorana P.C. Christopher P.
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