Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral adapting
Reexamination Certificate
1998-10-29
2001-10-30
Lee, Thomas (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral adapting
C710S062000, C710S065000, C710S120000, C710S120000, C708S551000, C712S225000, C370S471000
Reexamination Certificate
active
06311239
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to data transmission generally and, more particularly, to an architecture, circuitry and method for transmitting n-bit wide data over m-bit wide media.
BACKGROUND OF THE INVENTION
Conventional approaches for the binary transmission of a first bit width (e.g., a 10-bit wide) data over a second bit width (e.g., 8-bit transmission) media would be to use a 10-12-bit transmission code (i.e., TAXI). Another solution would be to use scrambler transmission codes which accept 10-bit wide parallel data as an input to the encoding or output of the decoding. Another approach would be to bypass the encoding altogether and transmit the 10-bits directly. This type of conventional approach requires the incoming data from the bus to have the proper transition density which the 8b10b encoding guarantees.
Conventional approaches place the responsibility of encoding or scrambling of data, to ensure meeting minimum transmission densities, on the user. Other transmission codes such as TAXI may not guarantee minimum transition densities in a situation where 8b10b decoding will provide such guarantees. Without a minimum density, the overall performance of the system may be inhibited.
SUMMARY OF THE INVENTION
The present invention concerns an architecture, circuitry and method for transmitting n-bit wide data over m-bit wide media that may comprise a first circuit configured to present a first series of data packets having a first bit-width in response to a second series of data packets having a second bit-width and a second circuit configured to present a third series of data packets having said first bit-width in response to said second series of data packets. The first circuit may comprise a buffer circuit configured to hold one or more of the first series of data packets and a packer circuit configured to present the second series of data packets in response to the data packets held in the buffer circuit. The second circuit may comprise an unpacker circuit configured to present the third series of data packets and a buffer circuit configured to hold one or more of the third series of data packets.
The objects, features and advantages of the present invention include providing a system solution for seamless transmission of N-bit (e.g., 10-bit) data words over M-bit (e.g., 8-bit) serial links using a byte oriented binary (i.e., serial) transmission code. The present invention may provide an efficient method for transmitting bit wide data requiring while using conventional 8b10b encoding/decoding schemes for serial portion of the transmission.
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Cypress Semiconductor Corp.
Lee Thomas
Maiorana P.C. Christopher P.
Schuster Katharina
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