Static information storage and retrieval – Read/write circuit – Including signal comparison
Reexamination Certificate
2001-04-05
2003-03-18
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including signal comparison
C365S210130
Reexamination Certificate
active
06535434
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to devices for operate with close to ground signals, in general, and to devices for sensing such a signal which is received from a memory cell, in particular.
BACKGROUND OF THE INVENTION
Memory devices, such as random access memory (RAM), read-only memory (ROM), non-volatile memory (NVM) and like, are known in the art.
These devices provide an indication of the data which is stored therein by providing an output electrical signal. A device called a sense amplifier is used for detecting the signal and determining the logical content thereof. U.S. Pat. No. 4,916,671 to Ichiguchi describes one such sense amplifier.
In general, prior art sense amplifiers determine the logical value stored in a cell by comparing the output of the cell with a threshold voltage level. If the output is above the threshold, the cell is determined to be erased (with a logical value of 1) and if the output is below the threshold, the cell is determined to be programmed (with a logical value of 0). The threshold level is typically set as a voltage level between the expected erased and programmed voltage levels which is high enough (or sufficiently far from both expected voltage levels) so that noise on the output will not cause false results. Typically, the expected erased and programmed voltage levels are 1.5V and 2.5V, respectively, and the threshold level is 2V.
Unfortunately, a high threshold level requires that the cell being sensed be given a sufficient amount of time to fully develop its signal thereby ensuring that, for an erased cell, the resultant signal has reached its full (high) voltage level. In order to achieve this in a reasonable amount of time, the entire array is first brought (or “equalized”) to a medium voltage level which the cell being sensed either increases (if it is erased) or decreases (if it is programmed). The equalization operation is time-consuming and requires a considerable amount of power.
The aforementioned U.S. Pat. Nos. 6,134,156 and 6,128,226 describe an alternative circuit architecture in which a reference cell is used in lieu of a fixed threshold voltage value. The architecture of those patents calls for a timing cell to accompany the reference cell in order to ensure that the sensing decision is made when the signal levels have reached a sufficient value at the input of the sense amplifier. This sensing scheme permits data retrieval at very low voltages, but is attendant with limitations. For example, certain read conditions such as a read cycle after an idle state and the situation in which the same word line is selected in consecutive read cycles (a read within read or “RWR” condition), can result in the word line voltage of the reference cell being either higher or lower than the word line voltage of the array cell. Consequently, the result of the comparison of the array and reference cell signals may differ during different read cycles. This situation may be avoided if enough time is allotted to the array cell and reference cell word lines to permit them to settle to their final levels. This greater time allotment, however, translates into a sacrifice in performance.
What is needed in the art is an improved sensing scheme and circuit architecture which reduces margin loss. The present invention satisfies this and other needs.
SUMMARY OF THE PRESENT INVENTION
The present invention provides a circuit architecture and sensing scheme in which the word line voltage applied to the operative reference cell is stable, and behaves the same way during all read cycles, regardless of the purpose of the read. Thus, a constant, non-zero word line voltage can be applied to the gate of a plurality of reference cells, each of which is configured as a reference against a prescribed operation such as a read operation, a program verify operation, an erase verify operation, or any other read operation (generally referred to herein as “read operations”). Consequently, there is no strobe signal applied to the reference cell.
According to one aspect of the present invention, a method for sensing a close to ground signal received from an array cell within a memory array is provided. The method includes the steps of providing a reference unit with a reference cell having a similar structure and a similar current path therethrough to that of the array cell and having a non-strobed word line voltage applied thereto. This method includes the additional steps of first discharging the array and the reference cell and then generating an array cell signal from the array cell and a reference signal from the reference cell. Further, a timing unit is provided that is operative to generate a digital timing signal that changes its state (e.g., changes from 0 volts to Vdd) when the reference signal reaches a predetermined level. A digital read signal is generated and output by the timing unit from the difference between the cell signal and the reference signal once the digital timing signal has been generated. The reference unit has a prescribed reference capacitance that can be equal to or can be a multiple of the expected capacitance of a bit line of the array.
According to another aspect of the present invention, an apparatus for sensing a close- to-ground array cell signal received from an array cell within a memory array is provided. The apparatus includes a reference unit, a timing unit and a differential comparator. The reference unit has reference cells whose structures emulate the response of an array cell and a reference capacitance that is equal to the expected capacitance of a bit line of the array. The reference cells are driven by a non-strobed word line voltage. The timing unit is operative to generate a digital timing signal. The differential comparator generates a digital read signal from the difference of the cell and reference signals once the timing signal is generated.
In a preferred implementation, the word line decoder of the memory array is free running (i.e., it has no strobe signal and a word line is always selected according to the address inputs). Furthermore, the word line voltage applied to the reference cell has the same value as the word line voltage supply applied to the selected array cell. In this implementation, a read cycle accessing an already selected word line (i.e., no X-address change) results in the word line voltage of the reference cell being identical to that of the array cell. At the opposite extreme, in which at least one X-address has changed, the preferred implementation presents a well-defined worst case scenario in terms of margin loss. A read cycle accessing an unselected word line will have a ramping array cell word line voltage compared to a reference cell having a constant word line voltage. Therefore, the array word line will never be higher than the reference word line. As a direct result, any margin loss that may exist, if any, will only affect readings of cells in the erased state. There will be no margin loss introduced for reading cells in the programmed state. Also, the second scenario described above defines the time at which sensing can safely start for that worst case situation. This differs from prior art methods and apparatus using a strobed X-decoder and a strobed word line since in those cases different types of read cycles could result in a margin loss for cells in either the erased or programmed states. Moreover, the worst case situation to determine the time at which sensing can safely start is not well defined in prior art schemes, thereby requiring an artificial timing margin to be introduced which sacrifices performance.
The inventive method and architecture can be utilized with a memory array, a sliced array having one or more columns of memory cells, and with redundant or auxiliary arrays.
REFERENCES:
patent: 4916671 (1990-04-01), Ichiguchi
patent: 5142495 (1992-08-01), Canepa
patent: 5335198 (1994-08-01), Van Buskirk et al.
patent: 5381374 (1995-01-01), Shiraishi et al.
patent: 5544116 (1996-08-01), Chao et al.
patent: 5627790 (1997-05-01), Golla et al.
patent: 57711
Eitan Boaz
Eliyahu Ron
Maayan Eduardo
Sofer Yair
Eitan Pearl Latzer & Cohen-Zedek
Nguyen Tan T.
Saifun Semiconductors Ltd.
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