Architecture and related methods facilitating secure port...

Details Architecture and related methods facilitating secure port... Architecture and related methods facilitating secure port...

2000-08-14

2003-11-11

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output command process

C710S029000, C711S138000, C712S225000

Reexamination Certificate

active

06647433

ABSTRACT:

TECHNICAL FIELD
This invention generally relates to data networks and, more particularly, to an architecture and related method(s) facilitating secure port bypass circuit (PBC) settings within a data network.
BACKGROUND
Port bypass circuits (PBC) are well known as a reliable means of switching in high-speed data networks. Simplistically speaking, a PBC is a multiplexer that is used within data networks to selectively couple network elements. Port bypass circuits possess several performance attributes such as low-latency switching and minimal jitter accumulation that make them particularly attractive for use in high-speed switching applications. PBCs are often employed to selectively couple network elements to a high-speed data network, drives within a redundant array of independent disks (RAID) system and/or their progeny (e.g., just a bunch of disks (JBOD), storage area networks (SANs)), and the like. An example prior art implementation of a PBC within a distributed storage system is presented with reference to FIG.
1
.
FIG. 1
illustrates a block diagram of an example PBC implementation within a distributed storage system
100
. For purposes of illustration, the example implementation is a RAID system
100
, wherein the PBC's are utilized to selectively couple storage devices to the storage system. As shown, the storage system
100
includes a bus controller
102
coupled to controller
104
(e.g., a backplane controller) via a control bus
106
. The backplane controller
104
is coupled to each of the Port Bypass Circuits
110
A . . . N via at least one enable line
108
A . . . N. As introduced above, the PBC's
110
A . . . N are utilized to selectively enable/disable an input/output device (e.g., storage device)
112
A . . . N to the RAID system
100
. It is to be appreciated that any of a number of alternate networking technologies such as, for example, Ethernet, Fast Ethernet, Gigabit Ethernet, Fibre Channel, etc., may well be used to transfer information within network
100
.
In accordance with the illustrated implementation, the bus controller
102
selectively issues instructions to the backplane controller
104
to engage/disengage one or more drives
112
A . . . N (e.g., enabling/disabling of a control line on the PBC) from the system
100
via the control bus
106
. Based on the control commands received from the bus controller
102
, backplane controller selectively enables one ore more PBCs
110
A . . . N by asserting an associated enable line
108
A . . . N. In accordance with a typical implementation, the control bus
106
is an addressable serial bus such as, for example, an I
2
C™ serial bus (introduced by Philips, N.A.), and the bus controller
102
is a bus bridge with I
2
C™ control facilities. In addition, loopback paths are typically implemented in the communication network using the PBC to enable self-testing and troubleshooting of the storage system
100
.
One shortcoming of such prior art systems, however, is a lack of programmatic capability at the PBC controller (e.g., the backplane controller of the example RAID system
100
). This lack of programmatic intelligence in the backplane controller
104
typically prohibits the use of any “protocol layer” in the control path
106
to ensure data integrity in setting the PBC states. Accordingly, invalid control data caused by noise, a fault in the communication path, I/O errors between controllers
102
and
104
, and the like can cause erroneous setting of one or more PBCs
110
A . . . N. The resultant undesirable PBC setting is unpredictable and not readily detectable in prior art implementations. Indeed, erroneous setting of a PBC state will typically result in enabling undesired data to stray onto the network communication paths that, at best, causes performance degredation and, at worst, breaks the data path which may require re-arbitration of device(s) or even a re-initialization of the network (e.g., RAID system) to re-establish the communication path.
SUMMARY
In accordance with the teachings of the present invention, an architecture and related methods facilitating secure port bypass circuit settings is presented incorporating the teachings of the present invention. According to a first implementation, a method for securing port bypass circuit settings is presented comprising issuing one or more command(s) to one or more inputs of a general purpose input/output (GPIO) system, wherein the command(s) cause a first output of the GPIO system associated with a first input of the multiple inputs to issue a control signal to a latch associated with a port bypass circuit (PBC) addressed in the received command(s), and a second output of the GPIO system associated with a second of the multiple inputs of the GPIO system to issue a clock signal to a latch associated with a PBC addressed in the received command(s). If command(s) received at the first and second inputs are consistent with changing a common PBC, the control signal and the clock signal are sent to a single latching device, which latches the control signal to the addressed PBC changing the state of the PBC. If the command(s) are not consistent with changing a common PBC, the control and clock signal(s) are not received by a common latch, and none of the PBC states change. According to one exemplary implementation, the signals must also be sent in the order denoted above, i.e., control signal then clock signal in order to effectively change the state of the targeted PBC. In this regard, the claimed invention presents an innovative system and method for securing port bypass circuit settings.
According to one implementation, a method is presented comprising issuing one or more control command(s) to a controller which, when interpreted, causes the controller to issue control signals to a port bypass circuit to control an operational state of the port bypass circuit. Upon verifying that the controller accurately received the one or more control commands, the control signals are passed to the port bypass circuit.


REFERENCES:
patent: 4355389 (1982-10-01), Sato et al.
patent: 5109190 (1992-04-01), Sakashita et al.
patent: 5448575 (1995-09-01), Hashizume
patent: 5703884 (1997-12-01), Ozaki
patent: 5812754 (1998-09-01), Lui et al.
patent: 6005819 (1999-12-01), Shin
patent: 6356984 (2002-03-01), Day et al.

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