Architecture and/or method for using input/output affinity...

Details Architecture and/or method for using input/output affinity... Architecture and/or method for using input/output affinity...

2006-05-09

2006-05-09

Whitmore, Stacy A. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C438S048000, C257S324000

Reexamination Certificate

active

07043703

ABSTRACT:
An apparatus comprising (i) one or more input/output cells, (ii) one or more hard macros and (iii) one or more input/output affinity regions. The one or more input/output affinity regions may be disposed between the one or more input/output cells and the one or more hard macros. Each of the one or more input/output affinity regions may be customized as (i) circuitry in a first mode and (ii) routing between the one or more input/output cells and the one or more hard macros in a second mode.

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