Architecture and method for partially reconfiguring an FPGA

Details Architecture and method for partially reconfiguring an FPGA Architecture and method for partially reconfiguring an FPGA

2000-07-25

2003-02-25

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C326S039000

Reexamination Certificate

active

06526557

ABSTRACT:

TECHNICAL FIELD
This invention relates to integrated circuits, particularly programmable logic devices or field programmable gate arrays (FPGAs). More particularly, this invention relates to techniques for partially reconfiguring sections of an FPGA without affecting other sections of the FPGA.
BACKGROUND OF THE INVENTION
Field programmable gate arrays (FPGAs) are configured to perform particular functions by loading a stream of bits, or bitstream, into a memory that controls configuration of configurable logic blocks (CLBs). Each CLB includes configurable logic, horizontal and vertical line segments that connect across adjacent cells to form interconnect lines, and a routing or switching structure to selectively connect the logic to the line segments.
It is sometimes desirable to change the functionality of the FPGA by reconfiguring some or all of the logic blocks. In the past, reconfiguration involved reprogramming the entire FPGA by loading a complete new bitstream into the FPGA to reconfigure all of the CLBs.
As FPGAs have grown rapidly in size, partial reconfiguration techniques have evolved to enable reconfiguration of selected portions of the FPGA without affecting other portions of the same FPGA. Due to the architecture of FPGAs, however, partial reconfiguration has been traditionally limited to reconfiguring entire columns of memory for controlling CLBs.
FIG. 1
shows an FPGA
20
to illustrate the limitations of conventional partial reconfiguration. The FPGA
20
has an array of tiles, each tile comprising configurable logic and related interconnect, which are collectively referred to as a configurable logic block (CLB)
22
. For illustration purposes, only a few CLBs are shown in FIG.
1
and only a few of the interconnect lines have been drawn. Typically, an FPGA
20
is implemented with thousands of repeatable CLBs
22
, each having many horizontal and vertical line segments. Young, Chaudhary and Bauer in U.S. Pat. No. 5,914,616 describe such a structure in more detail, and this patent is incorporated herein by reference.
Each CLB
22
has configurable logic, horizontal and vertical line segments that connect across adjacent cells to form interconnect lines, and a routing or switching structure to selectively connect the logic to the line segments. Configuration of the logic and connection between line segments is controlled by a configuration memory, into which a configuration is loaded for enabling the logic and interconnect lines to perform a desired function. In some FPGAS, data in the configuration memory is loaded by addressing sections of configuration memory on address lines and applying data to data lines. In some FPGAs, a frame of configuration data is fed serially into a shift register, then shifted in parallel to an addressed column of configuration memory cells. Vertical wires form address lines, as represented by address lines
24
, that generally span the height of the FPGA. Horizontal wires form configuration data lines, as represented by data lines
26
, that usually span the width of the FPGA.
In the FPGA of
FIG. 1
, configuration data from the bitstream is placed onto the data lines
26
by a shift register
28
. The bitstream contains frames of data, where each frame fills the shift register
28
and is used to program one column of memory cells accessed by a corresponding address line. As an example, the shift register
28
might hold a frame consisting of several thousands bits. The bitstream also contains commands to load a corresponding data frame into the shift register and once loaded, commands to select the appropriate address line associated with the data frame.
After an entire frame is loaded into the shift register
28
, the data bits may be temporarily transferred to a shadow register
30
so that the shift register
28
is free to begin receiving the next frame of data while the current data is being written. An address line is selected to transfer the data from the shadow register
30
via the data lines
26
into selected memory cells of the CLBs. This process is repeated for all address lines
24
to fully program the CLBs
22
on the FPGA
20
.
Using conventional methods, FPGA
20
can be partially reconfigured by shifting data bits into the shift register
28
and selecting only the address lines
24
of the CLBs
22
that are being reprogrammed. Unfortunately, since the address lines
24
span entire columns of CLBs
22
, all of the CLBs connected by the common address lines
24
are reconfigured, whether or not the programmer wants to change all blocks. This is represented pictorially in
FIG. 1
as a partial reconfiguration zone
32
.
As FPGAs continue to increase in size and complexity, it would be desirable and advantageous to partially reconfigure smaller sections of the FPGA that include less than all of the CLBs connected to a common address line. Accordingly, there is a need for an improved process or architecture that enables partial reconfiguration of selectable CLBs on the FPGA.
SUMMARY OF THE INVENTION
This invention concerns an FPGA architecture and method that enables partial reconfiguration of selectable configurable logic blocks (CLBs) connected to one or more address lines, without affecting other CLBs connected to the same address lines.
According to one implementation, partial reconfiguration at a memory cell resolution is achieved by manipulating the input voltages applied to the address and data lines of an FPGA configuration memory. These voltages are controlled in such a manner that certain memory cells within selected CLBs are programmed while other memory cells of the same or other CLBs connected to the same address line are not programmed. A mask register and additional mask lines are added to the FPGA to designate which data lines receive the programming voltages and which data lines receive voltages to prevent programming.
According to another implementation, partial reconfiguration at a CLB resolution is achieved by hardwiring the FPGA to enable selection of individual CLBs for reconfiguration purposes. In this implementation, the FPGA is equipped with a CLB control register, horizontal CLB control lines addressed by the CLB control register, and an extra set of address lines in addition to existing address lines. The CLB control lines and extra address lines are used to access the existing local address lines to enable selection and reconfiguration of individual CLBs without affecting other CLBs.
In another implementation, partial reconfiguration is at a resolution of one word, where a word is typically smaller than one dimension of a CLB. Thus, typically to reconfigure one CLB of the FPGA, several words in one column are replaced, and several columns that serve the CLB have at least some words that are replaced. However, the invention is not limited to one particular resolution. Any resolution can benefit from the principles of the invention.


REFERENCES:
patent: 5670897 (1997-09-01), Kean
patent: 5914616 (1999-06-01), Young et al.
patent: 6020758 (2000-02-01), Patel et al.
patent: 6057704 (2000-05-01), New et al.
patent: 6091263 (2000-07-01), New et al.
patent: 6102963 (2000-08-01), Agrawal
patent: 6262596 (2001-07-01), Schultz et al.
Kang et al., CMOS Digital Integrated Circuits: Analysis and Design, 1999, 2nd Edition, pp 417-435.

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