Electronic digital logic circuitry – Multifunctional or programmable – Array
Patent
1997-08-12
2000-04-18
Santamauro, Jon
Electronic digital logic circuitry
Multifunctional or programmable
Array
326 39, H03K 19177
Patent
active
060519916
ABSTRACT:
An architecture and distributed hierarchical interconnect scheme for field programmable gate arrays (FPGAs). The FPGA is comprised of a number of cells which perform logical functions on input signals. Programmable intraconnections provide connectability between each output of a cell belonging to a logical cluster to at least one input of each of the other cells belonging to that logical cluster. A set of programmable block connectors are used to provide connectability between logical clusters of cells and accessibility to the hierarchical routing network. An uniformly distributed first layer of routing network lines is used to provide connections amongst sets of block connectors. An uniformly distributed second layer of routing network lines is implemented to provide connectability between different first layers of routing network lines. Switching networks are used to provide connectability between the block connectors and routing network lines corresponding to the first layer. Other switching networks provide connectability between the routing network lines corresponding to the first layer to routing network lines corresponding to the second layer. Additional uniformly distributed layers of routing network lines are implemented to provide connectability between different prior layers of routing network lines. An additional routing layer is added when the number of cells is increased as a square function of two of the prior cell count in the array while the length of the routing lines and the number of routing lines increases as a linear function of two. Programmable bi-directional passgates are used as switches to control which of the routing network lines are to be connected.
REFERENCES:
patent: 4020469 (1977-04-01), Manning
patent: 4700187 (1987-10-01), Furtek
patent: 4736333 (1988-04-01), Mead et al.
patent: 4847612 (1989-07-01), Kaplinsky
patent: 4870302 (1989-09-01), Freeman
patent: 4918440 (1990-04-01), Furtek
patent: 4935734 (1990-06-01), Austin
patent: 4992680 (1991-02-01), Benedetti et al.
patent: 5144166 (1992-09-01), Camarota et al.
patent: 5204556 (1993-04-01), Shankar
patent: 5208491 (1993-05-01), Ebeling et al.
patent: 5221865 (1993-06-01), Phillips et al.
patent: 5243238 (1993-09-01), Kean
patent: 5260610 (1993-11-01), Pedersen et al.
patent: 5296759 (1994-03-01), Sutherland et al.
patent: 5298805 (1994-03-01), Garverick et al.
patent: 5329470 (1994-07-01), Sample et al.
patent: 5396126 (1995-03-01), Britton et al.
patent: 5455525 (1995-10-01), Ho et al.
patent: 5457410 (1995-10-01), Ting
patent: 5469003 (1995-11-01), Kean
patent: 5477067 (1995-12-01), Isomura et al.
patent: 5519629 (1996-05-01), Snider
patent: 5550782 (1996-08-01), Cliff et al.
patent: 5552722 (1996-09-01), Kean
patent: 5572148 (1996-11-01), Lytle et al.
patent: 5581199 (1996-12-01), Pierce et al.
patent: 5581767 (1996-12-01), Katsuki et al.
ATMEL Field Programmable Arrays, AT6000 Series, 1993, p. 1-16.
Altera Flex EPF81188 12,000-Gate Programmable Logic Device, Sep. 1992, ver. 1, p. 1-20.
Wescon/93 Conference Record, Sep. 28-30, 1993, ISBN 0-7803-9970-6, ORCA: A High Performance, Easy to Use SRAM Based Architecture, p. 310-320.
"Synthesis of Logic Functions on an Array of Integrated Circuits", L.M. Spandorfer, Contract No. AF 19(628)2907, Project No. 4645, Task No. 464504, Final Report, Nov. 30, 1965.
"Survey of Microcellular Research", Robert C. Minnick, Journal of the Association for Computing Machinery, vol. 14, No. 2, Apr. 1967, pp. 203-241.
"A High Performance FPGA with Hierarchical Interconnection Structure", Ping-Tsung Wang, Kun-Nen Chen, Yen-Tai Lai, May 30, 1994 IEEE International Symposium on Circuits and Systems, vol. 4 of 6, VLSI, p. 239-242.
"Dynamically Reconfigurable Devices Used to Implement a Self-Tuning, High Performances PID Controller", E. Buffoli, N. Scarabottolo, R. Scattolini, M. Tacchini, 1989 IEEE, p. 107-112.
"Boolean Decomposition of Programmable Logic Arrays", Srinivas Devadas, Albert R. Wang, A. Richard Newton and Alberto Saugiovanni-Vincentelli, IEEE 1988, p. 2.5.1-2.5.5.
"Implementing Neural Nes with Programmable Logic", Jacques J. Vidal, IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. 36, No. 7, Jul. 1988, p. 1180-1190.
Wescon/93 Conference Record, ISBN 0-7803-9970-6, "A High Performance Fine-Grained Approach to SRAM Based FPGAs", Fred Zlotnick, Paul Butler, Wanhao Li, Dandas Tang, p. 321-326.
Motorola Product Brief, Sep. 27, 1993, 4 pgs.
Proceedings of the IEEE 1993 Custom Integrated Circuits Conference, May 9-12, 1993, "Optimized Reconfigurable Cell Array Architecture for High-Performance Field Programmable Gate Arrays", Barry K. Britton, Dwight D. Hill, William Oswald, Nam-Sung Woo, Satwant Singh, p. 7.2.1-7.2.5.
Proceedings of the IEEE 1993 Custom Integrated Circuits Conference, May 9-12, 1993, "A Dual Granularity and Globally Interconnected Architecture for a Programmable Logic Device", Richard Cliff, Bahram Ahanin, L. Todd Cope, Frank Heile, Ricky Ho, Joseph Huang, Craig Lytle, Shamin Mashruwala, Bruce Pedersen, Rina Raman, Srinivas Reddy, Vinita Singhal, C.K. Sung, Kerry Veenstra, Anil Gupta, IEEE 1993, p. 7.3.1-7.3.5.
"Fine-Grain FPGA Architecture Uses Four Levels of Configuration Hierarchy", 2328 Electronic Design, 41 Oct. 1, 1993, No. 20 , Cleveland, OH, p. 33-34.
The Programmable Gate Array Data Book, Xilinx, 1992, p. 1-1--8-8.
BTR, Inc.
Santamauro Jon
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