Architecture and interconnect scheme for programmable logic...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000, C716S030000

Reexamination Certificate

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07409664

ABSTRACT:
An architecture of hierarchical interconnect scheme for field programmable gate arrays (FPGAs). A first layer of routing network lines is used to provide connections amongst sets of block connectors where block connectors are used to provide connectability between logical cells and accessibility to the hierarchical routing network. A second layer of routing network lines provides connectability between different first layers of routing network lines. Additional layers of routing network lines are implemented to provide connectability between different prior layers of routing network lines. An additional routing layer is added when the number of cells is increased as the prior cell count in the array increases while the length of the routing lines and the number of routing lines also increases. Switching networks are used to provide connectability among same and different layers of routing network lines, each switching network composed primarily of program controlled passgates and, when needed, drivers.

REFERENCES:
patent: 3473160 (1969-10-01), Wahlstrom
patent: 4020469 (1977-04-01), Manning
patent: 4207556 (1980-06-01), Sugiyama et al.
patent: 4642487 (1987-02-01), Carter
patent: 4661901 (1987-04-01), Veneski
patent: 4700187 (1987-10-01), Furtek
patent: 4706216 (1987-11-01), Carter
patent: 4720780 (1988-01-01), Dolecek
patent: 4736333 (1988-04-01), Mead et al.
patent: 4758745 (1988-07-01), Elgamal
patent: 4758985 (1988-07-01), Carter
patent: 4763020 (1988-08-01), Takata et al.
patent: 4786904 (1988-11-01), Graham, III et al.
patent: 4847612 (1989-07-01), Kaplinsky
patent: 4855619 (1989-08-01), Hsieh et al.
patent: 4870302 (1989-09-01), Freeman
patent: 4912342 (1990-03-01), Wong et al.
patent: 4918440 (1990-04-01), Furtek
patent: 4935734 (1990-06-01), Austin
patent: 4963770 (1990-10-01), Keida
patent: 4967107 (1990-10-01), Kaplinsky
patent: 4992680 (1991-02-01), Benedetti et al.
patent: 5012135 (1991-04-01), Kaplinsky
patent: 5122685 (1992-06-01), Chan et al.
patent: 5140193 (1992-08-01), Freeman, deceased et al.
patent: 5144166 (1992-09-01), Camarota et al.
patent: 5204556 (1993-04-01), Shankar
patent: 5208491 (1993-05-01), Ebeling et al.
patent: 5212652 (1993-05-01), Agrawal et al.
patent: 5220213 (1993-06-01), Chan et al.
patent: 5221865 (1993-06-01), Phillips et al.
patent: 5224056 (1993-06-01), Chene et al.
patent: 5225221 (1993-07-01), Camden et al.
patent: 5231588 (1993-07-01), Agrawal et al.
patent: RE34363 (1993-08-01), Freeman
patent: 5243238 (1993-09-01), Kean
patent: 5260610 (1993-11-01), Pederson et al.
patent: 5260611 (1993-11-01), Cliff et al.
patent: 5291079 (1994-03-01), Goetting
patent: 5296759 (1994-03-01), Sutherland et al.
patent: 5298805 (1994-03-01), Garverick et al.
patent: 5327023 (1994-07-01), Kawana et al.
patent: 5329470 (1994-07-01), Sample et al.
patent: 5331226 (1994-07-01), Goetting
patent: 5336950 (1994-08-01), Popli et al.
patent: 5341040 (1994-08-01), Garverick et al.
patent: 5343406 (1994-08-01), Freeman et al.
patent: 5371422 (1994-12-01), Patel et al.
patent: 5386354 (1995-01-01), Osteen
patent: 5396126 (1995-03-01), Britton et al.
patent: 5422833 (1995-06-01), Kelem et al.
patent: 5436575 (1995-07-01), Pedersen et al.
patent: 5457410 (1995-10-01), Ting
patent: 5469003 (1995-11-01), Kean
patent: 5477067 (1995-12-01), Isomura et al.
patent: 5483178 (1996-01-01), Costello et al.
patent: 5519629 (1996-05-01), Snider
patent: 5550782 (1996-08-01), Cliff et al.
patent: 5581767 (1996-12-01), Katuski et al.
patent: 5668771 (1997-09-01), Cliff et al.
patent: 5848005 (1998-12-01), Cliff et al.
patent: 6064599 (2000-05-01), Cliff et al.
patent: 6160420 (2000-12-01), Gamal
patent: 7078933 (2006-07-01), Ting
patent: 0415542 (1991-03-01), None
patent: 0 630 115 (1994-12-01), None
patent: 2180382 (1987-03-01), None
patent: 9208286 (1992-05-01), None
patent: 9410754 (1994-05-01), None
Spandorfer, L.M., “Synthesis of Logic Functions on an Array of Integrated Circuits,” Contract No. AF19 (628) 2907, Project No. 4645, Task No. 464504, Final Report, Nov. 30, 1965.
ATMEL Field Programmable Arrays, AT 6000 Series, 1993, p. 1-16.
Altera Corporation Date Sheet, Flex EPF81188 12,000 Gate Programmable Logic Device, Sep. 1992, V3er. 1, pp. 1-20.
Shoup, R.G., “Programmable Cellular Logic Arrays,” Abstract, Ph.D. Dissertation, Carnegie Mellon University, Pittsburgh, PA, Mar. 1970, (partial) pp. ii-121.
Britton, et al., “Optimized Reconfigurable Cell Array Architecture for High-Performance Field Programmable Gate Arrays,” Proceedings of the IEEE 1993 Custom Integrated Circuits Conference, 1993, pp. 7.2.1-7.2.5.
Buffoli, E., et al., “Dynamically Reconfigurable Devices Used to Implement a Self-Tuning, High Performances PID Controller,” 1989 IEEE, pp. 107-112.
Devades, S:, et al., “Boolean Decomposition of Programmable Logic Arrays,” IEEE 1988, pp. 2.5.1-2.5.5.
Vidal, J.J., “Implementing Neural Nets with Programmable Logic,” IEEE Transactions on Acoustic, Speech, and Sgianl Processing, vol. 36, No. 7, Jul. 1988, pp. 1180-1190.
Liu, D.L., et al., “Design of Large Embedded CMOS PLA's for Built-In Self-test,” IEEE Transactions on Computed-Aided Design, vol. 7, No. 1, Jan. 1988, pp. 50-53.
Sun, Y. et al., “An Area Minimizer for Floorplans with L-Shaped Regions,” 1992 International Conference on Computer Design, 1992 IEEEE, pp. 383-386.
Minnick, R.C., “A Survey of Microcellular Research”, vol. 14, No. 2, Apr. 1967, pp. 203-241.
Cliff et al., “A Dual Granularity and Globally Interconnected Architecture for a Programmable Logic Device”, IEEE '93 pp. 7.3.1-7.3..5.
Xilinx, “The Programmable Gate Array Data Book”, 1992.
Wescon '93, pp. 321-326.
Wescon '93, pp. 310-320.
Aggarwal, Aditya Kumar, “Routing Algorithms and Architectures for Hierarchical Field Programmable Gate Arrays,” Thesis: Univ. of Toronto, Canada, Jan. 1994 (99 pages).
Chow, Paul et al., “A 1.2 μm CMOS FPGA Using Cascaded Logic Blocks and Segmented Routing,” Department of Electrical Engineering, University of Toronto, Toronto, Ontario, Canada M5S 1A4 (12 pages), not dated.
Grunbacher, Herbert et al., “Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping,” Springer-Verlag, from Second International Workshop on Field-Programmable Logic and Applications, Vienna, Austria, Aug. 31-Sep. 2, 1992 (10 pages).
Ikawa et al., “A One Day Chip: An Innovative IC Construction Approach Using Electrically Reconfigurable Logic VLSI with On-Chip Programmable Interconnections,” IEEE Journal of Solid State Physics, vol. SC-21, Apr. 1986, pp. 223-227.
Shoup, Richard G. “Programmable Cellular Logic Arrays,” Computer Science Department, Carnegie-Mellon University, Mar. 1970.
Wahlstrom, Sven, “Programmable Logic Arrays-Cheaper by the Millions”, Electronics, Dec. 11, 1967, pp. 90-95.
XILINX “XC4000 Data Book, Logic Cell Array Family,” Dec. 1991 (65 pages).
XILINX “XC6200 Field Programmable Gate Arrays,” Apr. 24, 1997, Version 1.10 (73 pages).
Zlotnick et al., “A High Performance Fine-Grained Approach to SRAM Based FPGAs,” WESCON Conference Digest, Sep. 1993, pp. 321-326.
Aipla's Model Patent Jury Instructions, American Property Law Association, 2005.

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