Architecture and interconnect for programmable logic circuits

Details Architecture and interconnect for programmable logic circuits Architecture and interconnect for programmable logic circuits

1999-12-20

2001-11-20

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S040000, C326S039000, C326S038000

Reexamination Certificate

active

06320412

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to programmable logic circuits. More particularly, the present invention relates to an architecture and interconnect for programmable logic circuits.
2. Art Background
Programmable logic circuits such as field programmable gate arrays (FPGAs) provide an alternative mechanism and device to custom integrated circuits. Since its original inception, developments in the technology have lead to smaller die size and increased functionality. A number of interconnect approaches have implemented to interconnect the logic cells of an FPGA. One of the elements used in the interconnect of an FPGA is the switch which can be programmed either to conduct a signal connecting two wires or acting as an open. Early implementations provided a re-programmable logic array where a memory controlled switch was used.
The actual area on the die for the logic cells is generally just a fraction of the total area of the semiconductor device. Typically the area on the die used to implement a switch is relatively small compared to the area required for the memory cell used to control the switch with the memory cell and the switch forming the largest portion of the total core area of the die. Thus early technology attempted to address the goal of practically using the logic functions in a re-programmable gate array with the limited program controlled routing resources while keeping the die size small enough.
A preferred way to implement a logic function in FPGAs is to have the input/output of a logic cell connectable to every other logic cell; however, this is not practical for memory controlled programmable logic arrays due to the amount of die space the memory cells require. Weighing out the different factors, a number of approaches provide that the logic cell is connectable to a limited number of other logic cells and a small set of routing resources through a program control means. If a logic cell can not be program-controlled to connect directly to the desired logic cells, the routing resources are then used to achieve indirect connection, either though other routing resources or logic cells.
In U.S. Pat. No. 5,457,410 an architecture was described where a local routing resource referred to as the I-Matrix was used to interconnect a cluster of logic cells. The I-Matrix consists of both routing lines and switches to select the desired connections. The I-Matrix routing lines have the ability to connect to neighboring I-Matrix routing lines, again through the switches, hence allowing logic cells to be connectable not just inside a local cluster but adjacent clusters.
The I-Matrix allows the formations of medium sized macro functions with short, fast interconnects which are typically characterized as low fanout (e.g. a signal originating from an output of a logic cell to one or two inputs of other logic cells). The architecture also provides the concept of a block connector that can function as the input/output ports of the macro functions, in addition to being the routing resources interconnecting logic cells. A block connector also has the ability to extend to the adjacent logical blocks through programmed controlled switches.
With block connectors functioning as program selectable ports, they may be interfaced to MLA routing lines, through a bi-directiona MLA1 exchange network called referred to as Block Connector (BC) Tabs. The block connectors in one logical block are programmably connectable to MLA routing lines which in turn are connectable to other block connectors of other logical blocks and to other MLA routing lines through the Block Connector Tabs. Drivers improve the speed of the circuits through the BC Tabs which eliminates the need to design large drivers inside the logic cells as is typical of other routing networks.
In PCT WO95/04639, an alternative scheme was disclosed wherein two adjacent blocks shared a common set of different levels of MLA routing lines. Significant sized circuits can be formed, for example, in a MLA3 (M3) region (which may be, for example, 4×8 logical blocks or 8×8 logical blocks). Furthermore, the MLA Tabs similar to the BC Tabs may be included at the third hierarchical level of higher level routing lines to interface to routing lines at a fourth level and above. MLA Tab routing lines may be viewed as similar to third level routing lines except that the MLA Tabs routing lines are a subset which interfaces to yet higher levels of routing resources through the Tab Networks
SUMMARY OF THE INVENTION
An improved programmable logic device and interconnect architecture is provided. In one embodiment an interconnect network provides programmable routing between cells. In one embodiment the interconnect network includes first routing lines of a first level of routing lines, second routing lines of a second level of routing lines and third routing lines of a third level of routing lines. The first and second routing lines are programmably and bidirectionally coupled to the third routing lines such that signals are selectively driven from either the first or second routing lines to the third routing lines and signals are selectively driven from the third routing lines to the first routing lines and second routing lines.


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