Architecture and fabrication method of a vertical memory cell

Details Architecture and fabrication method of a vertical memory cell Architecture and fabrication method of a vertical memory cell

2006-06-20

2006-06-20

Ho, Tu-Tu (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S302000

Reexamination Certificate

active

07064373

ABSTRACT:
A vertical memory cell comprises a storage capacitor, the inner electrode of which is formed in a deep trench, and a vertical selector transistor. The selection transistor has an upper source/drain region and a lower source/drain region, which has emerged by outdiffusion of a dopant from the inner electrode. A gate electrode, which in each case controls a current flow between two assigned source/drain regions, is formed, in segments, as a segment of an addressing line arranged row-wise in active trenches. The provision of an auxiliary structure in the active trenches enables the addressing lines to be vertically positioned in the active trenches independently of a depth of the active trenches. Leakage currents which occur in overlap regions of the addressing lines with the inner electrode or the lower source/drain region are reduced.

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