Electrical computers and digital processing systems: processing – Processing control – Branching
Patent
1996-10-18
1999-09-28
Pan, Daniel H.
Electrical computers and digital processing systems: processing
Processing control
Branching
713502, 712 32, G06F 940, G06F 944, G06F 938
Patent
active
059580488
ABSTRACT:
For certain classes of software pipelined loops, prologue and epilogue portions of adjacent inner loops in a nested loop can be overlapped. In this way, outer loop code, as well as inner loop code, can be software pipelined. Architectural support for software pipelined nested loops is provided by a set of loop parameter and status registers and by an implementation of loop state dependent, multiway control transfers. For loop body code compatible with two simple constraints, the present invention does not require additional code elements for disabling garbage operations during prologue and epilogue loop periods of adjacent inner loops. Nested loop control allows overlap between the epilogue period of a prior inner loop and the prologue period of a next inner loop. As a result, nested loop code can be more efficiently scheduled by a compiler for execution on a processor such as VLIW processor which provides architectural support for software pipelined nested loops, thereby providing improved loop performance. Loop state dependent, multiway control transfers are provided by multi-way control transfer logic which includes the loop parameter and status registers and a branch target selector for selecting control transfer addresses corresponding to inner loop body code, a start patch, and a finish patch from control transfer address registers in accordance with loop state.
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Babaian Boris A.
Gruzdov Feodor A.
Sakhin Yuli Kh.
Volin Vladimir S.
Volkonski Vladimir Yu.
Elbrus International Ltd.
Pan Daniel H.
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