Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2007-10-23
2007-10-23
Beausoliel, Robert (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S010000, C714S012000
Reexamination Certificate
active
10819241
ABSTRACT:
In one aspect of the present invention, a circuit is provided which implements an instruction set architecture defining a first instruction group, a second instruction group to enter a high-reliability mode of operation, and a third instruction group to enter a non-high-reliability mode of operation. The circuit includes means for causing the circuit to enter the high-reliability mode of operation in response to receiving the second instruction group; means for causing the circuit to enter the non-high-reliability mode of operation in response to receiving the third instruction group; first execution means for executing the first instruction group in the high-reliability mode of operation if the circuit is in the high-reliability mode of operation; and second execution means for executing the first instruction group in the non-high-reliability mode of operation if the circuit is in the non-high-reliability mode of operation.
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Intel Itanium Architecture Software Developer's Manual, vol. 3: Instruction Set Reference, Revision 2.1, Oct. 2002, Part 1, Chapter 3, http://www.intel.com/design/itanium/manuals/iiasdmanual.htm#instruction.
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Safford Kevin David
Soltis Jr. Donald Charles
Beausoliel Robert
Wilson Yolanda L
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