Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-06-13
2002-11-05
Phan, Trong (Department: 2818)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06477689
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention generally relates to electronic circuit fabrication. More particularly, the present invention relates to a computer-based method and architecture that automatically transforms a behavioral description of a circuit into a hardware level representation of the circuit.
2. Discussion
In order to fabricate an electronic circuit such as an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA), a number of time critical processes must be completed. For example, the first step is to design the circuit at a “behavioral” level. The behavioral level can be viewed as a top level of a hierarchy, in which the hardware level of the hierarchy characterizes the circuit in terms of actual hardware components and is positioned at the bottom of the hierarchy. The behavioral description therefore might be a block diagram or netlist that describes the various functions of the circuit in relatively general terms.
Characterizing the circuit at the hardware level based on the behavioral description is critical in the circuit fabrication process. This is because the generally described functions in the behavioral description do not have enough specificity to fully enable the circuit manufacturer to implement the design. The conventional approach is therefore to manually generate an electronic file that characterizes the circuit at the hardware level in a desired programming language such as the well-known hardware description language (HDL). Thus, a design engineer with intricate knowledge of the electronic principles contained in the circuit as well as the desired programming language must go through the behavioral description on a component-by-component basis and generate the necessary code sets in the desired programming language. It is easy to understand that such an approach is quite labor intensive and subject to human error. It is therefore desirable to provide a mechanism for automatically characterizing a circuit at a hardware level.
Once the electronic file has been manually generated, a complex verification process is also required. Thus, operation of the circuit is simulated by providing the electronic file with a set of predefined inputs. The simulation results are compared with known output values that should have resulted from the simulation process. In the case of the ASIC, a model of the circuit in the well known C programming language is also manually generated to provide a cross-verification mechanism. This is typically required due to the complex nature of the ASIC fabrication process and the resulting need for a high level of certainty as to the functionality of the electronic file. Once again, the manual generation of the C model requires detailed knowledge of the C programming language and results in a significant increase in the labor costs associated with the overall fabrication process. Once the electronic file has been verified, it is typically converted into a format that is conducive to the equipment of the manufacturer using one or more well-known conversion programs such as commercially available Synopsis. After the electronic file has been converted, the manufacturer can engage in various fabrication processes such as liquid or plasma etching in order to fabricate the circuit.
It will be appreciated that the above manual processes add to both the lead time and fabrication costs associated with the circuit. It is therefore desirable to provide a mechanism for mapping known circuit components to a code set for a desired programming language in order to characterize a circuit at a hardware level in the desired programming language based on a behavioral description of the circuit.
SUMMARY OF THE INVENTION
The above and other objectives are provided by a computer-implemented method for characterizing a circuit at a hardware level in accordance with the present invention. The method includes the step of receiving a description of the circuit, where the description characterizes the circuit at a behavioral level of a hierarchy. The method further provides for receiving a set of predefined computer-based commands requesting desired modifications in the description of the circuit. An electronic file is then generated based on the computer-based commands such that the electronic file characterizes the circuit at a hardware level in a desired programming language. The hardware level is at a lower level in the hierarchy than the behavioral level. The use of computer-based commands to automatically generate the electronic file reduces manual labor requirements to levels unachievable through conventional approaches.
Further in accordance with the present invention, a computer-implemented method for generating an electronic file is provided. The method includes the step of implementing desired modifications in a description of a circuit with a set of predefined modules based on computer-based commands and a library of foundry primitives. The foundry primitives map known components to code sets for a desired programming language. A hierarchical netlist is also generated, where the hierarchical netlist represents the circuit at each level in a hierarchy. The method further provides for repeatedly updating the hierarchical netlist in accordance with the modifications.
In another aspect of the invention, a computer-implemented design tool architecture is provided. The architecture includes a medium for storing a description of an application specific integrated circuit (ASIC), where the description describes the ASIC at a behavioral level of a hierarchy. The architecture further includes a library of foundry primitives and a command interpreter. The foundry primitives map known ASIC components to code sets for a hardware description language (HDL). The command interpreter generates an electronic file based on a set of predefined computer-based commands such that the electronic file characterizes the circuit at a hardware level. The hardware level is at a lower level in the hierarchy than the behavioral level.
It is to be understood that both the foregoing general description and the following detailed description are merely exemplary of the invention, and are intended to provide an overview or framework for understanding the nature and character of the invention as it is claimed. The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute part of this specification. The drawings illustrate various features and embodiments of the invention, and together with the description serve to explain the principles and operation of the invention.
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Berman Arnold L.
Mandell Michael I
Harness & Dickey & Pierce P.L.C.
Phan Trong
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