Architectural power estimation method and apparatus

Data processing: measuring – calibrating – or testing – Measurement system in a specific environment – Electrical signal parameter measurement system

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702 57, 702117, 364490, 364578, 39518313, 371 271, 371 274, G06F 11263

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active

059407794

ABSTRACT:
A method (100) and apparatus (600) estimates power of an architectural design. Power functions are generated (step 102) for standard components (20) by synthesizing to a power-measurable implementation (step 202). A behavioral description is simulated (step 106) to produce switching activity and then parsed (step 108) to compute power from power functions of instantiated standard components (steps 109, 114, 118) from switching activity (step 116). Behavioral operations are parsed (step 108) into short and long blocks based on the number of operations. Short blocks are precompiled (step 110) to produce an RTL implementation including standard components. Power is estimated from switching activity at ports and inferred nodes (step 420). Long blocks are synthesized to produce power-measurable implementations (step 112). Power is estimated with a power function from weighted switching activity at each input (steps 508, 512-514).

REFERENCES:
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patent: 5668732 (1997-09-01), Khouja et al.
patent: 5673420 (1997-09-01), Reyes et al.
F. Najm, "Transition Density, A Stochastic Measure of Activity in Digital Circuits", 28th ACM/IEEE Design Automation Conference, Paper 38.1, Jul. 1991, pp. 644-649.

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