Arbitration technique based on processor task priority

Details Arbitration technique based on processor task priority Arbitration technique based on processor task priority

2005-01-25

2005-01-25

Auve, Glenn A. (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S306000

Reexamination Certificate

active

06848015

ABSTRACT:
A computer system including multiple CPUs inform other logic in a computer system as to the priority level (e.g., task priority) associated with the CPU or software executing thereon. The logic makes arbitration decisions regarding CPU transactions based, at least in part, on the task priorities of the various CPUs. The logic that implements this technique may be a host bridge within a computer system having multiple CPUs or in a switch or router that interconnects multiple nodes or computer systems.

REFERENCES:
patent: 5564060 (1996-10-01), Mahalingaiah et al.
patent: 5918057 (1999-06-01), Chou et al.
patent: 5956516 (1999-09-01), Pawlowski
patent: 6249830 (2001-06-01), Mayer et al.
patent: 20010032286 (2001-10-01), Pawlowski
patent: WO 9930243 (1999-06-01), None

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