Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output access regulation
Reexamination Certificate
1994-12-09
2002-08-13
Pan, Daniel H. (Department: 2183)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output access regulation
C710S035000, C710S021000, C710S045000, C710S061000, C710S112000, C710S117000, C710S118000, C711S168000, C711S146000, C711S150000
Reexamination Certificate
active
06434638
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates, in general to granting bus priority to a requesting subsystem and, in particular, to a protocol for establishing bus priority between competing systems on the same bus. More particularly still, the present invention relates to a zero-cycle arbitration protocol to allow point-to-point communication between two peer subsystems across the same bus line.
2. Description of the Related Art
Bus arbitration protocol and methods for arbitrating bus access are well known in the art. Typically, the arbitration method or protocol is designed so as to reduce the arbitration overhead when one of two subsystems continuously uses the system bus. The arbitration protocol also is used to guarantee fairness so as not to starve one of the subsystems from the bus system. Bus systems having multiple subsystems often use an arbitration mechanism to avoid bus contention.
One example of an arbitration system is one that decides who is sending and who is listening by way of a symmetrical protocol. Typically, three clock cycles are required in the symmetrical protocol where one cycle is used for sending a request, the second cycle is used for the arbitration, and the third cycle is used for the response with the proper selection. A second arbitration protocol uses a master-slave relationship where one system is the master and the other is the slave such that the slave always makes requests for the bus while the master arbitrates whether to grant bus access to the slave. Like the symmetrical protocol, the master slave system requires at least three clock cycles to perform arbitration and grant bus access to any subsystem.
Accordingly, what is needed is an arbitration system and method that reduces arbitration overhead while keeping the bus use fair to all subsystems on the bus system. Additionally, what is needed is a bus arbitration system that grants at least partial real-time bus access during bus request transmission by at least one of the subsystems on the bus system.
SUMMARY OF THE INVENTION
It is therefore one object of the present invention to provide a protocol for granting bus priority to a requesting subsystem.
It is another object of the present invention to provide the protocol for establishing bus priority between competing systems on the same bus.
It is yet another object of the present invention to provide to zero-cycle arbitration protocol to allow point-to-point communication between two peer subsystems across the same bus line.
The foregoing objects are achieved as is now described. According to the present invention, an arbitration protocol is provided for determining between a pair of subsystems within a networking system having a plurality of subsystems which subsystem might obtain access to a common hardware resource. The protocol allows the networking system to determine which subsystem becomes the sender and which becomes the receiver. The protocol is based on a point-to-point communication between two peer subsystems. It is based on an asymmetrical quality such that the first or priority subsystem has a zero latency in accessing the switch while the second subsystem must wait at least one clock cycle before obtaining access to the network system after requesting it and after the end of control by the first subsystem.
In the protocol, a subsystem can only initiate one transaction per cycle, but the subsystem may make consecutive uses of the common bus. Each use is separated by at least one idle cycle. When the bus is idle, the first subsystem transmits a signal requesting bus access If the second subsystem has not indicated in a previous cycle its own intentions to control the bus. The first subsystem will not transmit if the second subsystem has already indicated its intentions to control the bus. The second subsystem must prevent transmitting over the bus if it determines that the first subsystem has initiated a request for the bus system. Likewise, the second subsystem withholds transmitting until the first subsystem has ended its control of the bus system.
A second asymmetrical protocol is also provided, but delays access to the bus for the first subsystem in contrast to the first embodiment that has zero latency when the first subsystem requests access to the bus when it is available. The delayed action protocol is used for systems that are unable to process data simultaneously with requesting access to the bus, which processing is typically provided by a transparent latch needed for use in the zero-cycle arbitration protocol.
The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 4556310 (1985-12-01), Masuda et al.
patent: 4704606 (1987-11-01), Hasley
patent: 4811277 (1989-03-01), May et al.
patent: 4959775 (1990-09-01), Yonekura
patent: 4961140 (1990-10-01), Pechanek et al.
patent: 4987529 (1991-01-01), Craft et al.
patent: 5179709 (1993-01-01), Bailey et al.
patent: 5181201 (1993-01-01), Schauss et al.
patent: 5182800 (1993-01-01), Farrell et al.
patent: 5195185 (1993-03-01), Marenin
patent: 0 488 771 (1991-11-01), None
patent: 0 523 627 (1992-04-01), None
D. Gawlick, “Lock Processing in a Shared Data Base Enviornment”, IBM Technical Disclosure Bulletin, vol. 25, No. 10, Mar. 1983, pp. 4980-4985.
H. H. Sotolongo, “Multi-Processor Bus Distributed Arbitration with Centralized Fairness”, IBM Technical Disclosure Bulletin, vol. 34, No. 11, Apr. 1992, pp. 200-208.
R.G. Eikill, et al., “Distributed Main Store Bus Arbitration Algorithm and Tie Break Register”, IBM Technical Disclosure Bulletin, vol. 33, No. 4, Sep. 1990, pp. 294-296.
“Dual-Ported Bus Structure With Asynchronous DMA Handshake”, IBM Technical Disclosure Bulletin, vol. 28, No. 11, Apr. 1986, pp. 4782-4785.
W. Chapman, et al., “Bus Arbitration and Buffer Management”, IBM Technical Disclosure Bulletin, vol. 30, No. 11, Apr. 1988, pp. 387-391.
D.G. Bourke, et al., “Time Division Multiplesed Service Requesting”, IBM Technical Disclosure Bulletin, vol. 33, No. 1A, Jun. 1990, pp. 340-346.
D.F. Bantz, “Decentrilized Request Resolution Mechanisms”, IBM Technical Disclosure Bulletin, vol. 20, No. 2, Jul. 1977, pp. 853-855.
Donalk M. Chiarulli, et al. “Optical Bus Control for Distributed Multiprocessors”, Journal of Parallel and Distributed Computing, 10, 1990, pp. 45-54.
D. Carden, et al., “A Fast Image Bus, Display and Processing Enviornment of the Macintosh II”, Departmend of Electrical Engineering, University College, University of NSW, ADFA, Canberra ACT, pp. 197-200.
Thomas Wheatley, “Determining Bus Arbitration Policies and Data Transfer Techniques for Multiprocessor Systems”, National Institute of Standards and Technology, Gaithersburg, MD, IEEE, 1991, pp. 143-146.
T. Nakada, et al., “Bus Arbitration Method for A Two-Way Multiprocessor”, IBM Technical Disclosure Bulletin, vol. 35, No. 5, Oct. 1992, pp. 439-442.
D. Cocanougher, et al., “Two-Party Bus Arbitration for Floating-Point Operation”, IBM Technical Disclosure Bulletin, vol. 29, No. 11, Apr. 1987, pp. 4800-4801.
Bracewell & Patterson L.L.P.
International Business Machines - Corporation
Pan Daniel H.
Salys Casimer K.
LandOfFree
Arbitration protocol for peer-to-peer communication in... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Arbitration protocol for peer-to-peer communication in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Arbitration protocol for peer-to-peer communication in... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2917516