Arbitration of data transfer requests

Details Arbitration of data transfer requests Arbitration of data transfer requests

2007-07-03

2007-07-03

Bataille, Pierre-Michel (Department: 2186)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

C711S105000, C712S215000

Reexamination Certificate

active

10815961

ABSTRACT:
A data processor core10comprising: a memory access interface portion30operable to perform data transfer operations between an external data source and at least one memory120associated with said data processor core; a data processing portion12operable to perform data processing operations; a read/write port40operable to transfer data from said processor core to at least two buses75A,75B said at least two buses being operable to provide data communication between said processor core10and said at least one memory120, said at least one memory120comprising at least two portions120A,120B, each of said at least two buses75A,75B being operable to provide data access to respective ones of said at least two portions120A,120B; arbitration logic110associated with said read/write port40; wherein said arbitration logic is operable to route a data access request requesting access of data in one portion of said at least one memory received from said memory access interface to one of said at least two buses providing access to said one portion of said at least one memory and to route a further data access request requesting access of data in a further portion of said at least one memory received from said data processing portion to a further one of said at least two buses providing access to said further portion of said at least one memory, said routing of said data access requests being performed during the same clock cycle.

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IBM Technical Discl. Bulletin vol. 28 No. 12 May 1986, pp. 5329-5333, “High-Speed Processor Bus Arbitration”.
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