Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
2000-12-12
2004-04-13
Thai, Xuan M. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S119000, C710S120000, C710S121000, C710S306000, C710S309000, C710S313000, C710S314000, C710S113000, C710S114000
Reexamination Certificate
active
06721833
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a bus transaction method. More particularly, the present invention relates to a transaction method between the control chipsets in a computer system.
2. Description of Related Art
FIG. 1
is a block diagram showing a PCI bus system connecting various components of a conventional computer system. As shown in
FIG. 1
, a central processing unit
10
is coupled to the PCI bus
14
via a host bridge
12
. The master controller of several PCI compatible peripheral devices such as a graphic adapter
16
a
, an expansion bus bridge
16
b
, a LAN adapter
16
c
and a SCSI host bus adapter
16
d
can also be coupled to the PCI bus
14
. Each of these master controllers is able to send out a request (REQ) signal demanding the use of the PCI bus
14
. The host bridge
12
serves as an arbitrator that sends out grant (GNT) signals to the controller when the PCI bus
14
is available.
Data transmission between PCI compatible devices (such as the master controllers or the north bridge of a computer chipset) are controlled by a few interface control signals. A cycle frame (FRAME) is issued from an initiator (can be the master controller or the north bridge) indicating the initialization of a data access operation and the duration therein, As soon as the FRAME signal is out, data transaction via the PCI bus begins. A low potential for the FRAME signal indicates data transmission is in progress. After the initiation of data transaction, the address bus AD will send out a valid address during the address cycle. In the meantime, the command/byte enable (CBE[3:0]) signal lines will send out a valid bus command (according to PCI specification) so that the target device knows the data transaction mode demanded by the initiator. In general, the four bits of the command/byte enable signal lines are capable of coding tip to a maximum of 16 different commands, and each command is defined in detail in the PCI specification. After the effective address is out, a data cycle begins in which data is transmitted through the address bus AD. In the meantime, byte enable signals are sent so that data can be transmitted. When the transmission of FRAME signal stops, the last set of data is transmitted and no more in the current transaction An initiator ready (IRDY) signal and a target ready (TRDY) signal are also used by the system for displaying the readiness of the initiating device and the target device in data transaction. In a data read operation, the IRDY signal indicates that the initiator is ready to receive the demanded data. In a data write operation, the TRDY signal indicates that the target device is ready to receive the demanded data. A stop (STOP) signal is used by the target device to request a termination of data transaction from the initiator.
FIG. 2
is a timing diagram showing the various signals in the PCI bus interface during a read operation. The period within which data are transmitted via the PCI bus is known as a bus transaction cycle
20
. The bus transaction cycle
20
includes an address cycle
22
and several data cycles, for example,
24
a
,
24
b
and
24
c
. Each data cycle
24
a/b/c
can be further divided into a wait cycle
26
a/b/c
and a data transfer cycle
28
a/b/c
. The following is a brief description of the PCI bus interface during a read operation for illustrating the control signals according to PCI specification.
During cycle T
1
, a FRAME signal is sent by the initiator indicating the start of a data transaction while a start address is put on the address bus AD lines to locate the target device of the transaction. In the meantime, a read command is transmitted through the CBE lines. After the delivery of the read command, a byte enable signal is put on the CBE lines. The byte enable signals are sent throughout the data cycles (including
24
a
,
24
b
and
24
c
). During cycle T
2
, the initiator submits an initiator ready signal IRDY indicating its readiness for data transmission. However, the target device is still not ready yet. Hence, the target device keeps preparing the data while the initiator idles in the wait cycle
26
a
of the data cycle
24
a
. During cycle T
3
, the target device has prepared all the necessary data for transmission, thereby sending out a target ready TRDY signal. Therefore, in data cycle
28
a
, both IRDY and TRDY are out and so the initiator can begin to read data from the target device. During cycle T
4
, the target device no longer issues the target ready TRDY signal, which signals the end of the first set of transmission data, Meanwhile, a set of data is prepared inside the target device. Again, the initiator enters a wait cycle
26
b
within the data cycle
24
b
. During cycle T
5
, the target ready TRDY signal is issued indicating the second set of data is ready. The second set of data is ready by the initiator in cycle
28
b
when both the HEY and the TRDY signals are issued. When the initiator has insufficient time to read all the data from the target device as in cycle T
6
, the IRDY signal terminates. Since the TRDY signal is still out, the wait cycle
26
c
is activated by the initiator. As soon as the initiator is ready again as in cycle T
7
, the IRDY signal is re-issued. The initiator reads the data from the target device during data transfer cycle
28
c
when both IRDY and TRDY signals are issued, thereby completing a single read operation.
To carry out proper data transaction according to the conventional PCI specification, complicated control signals, wait states, arbitration steps must be used. Typically, up to 45 to 50 signaling pins are required according to the PCI specification. In general, complicated procedure is unnecessary for internal transaction between control chipsets. Hence, to speed up internal transaction between control chipsets, a simplified transaction method that adheres to the conventional PCI specification is needed.
However, transactions between control chips of a PC generally do not use all of the complicated functions provided by the PCI specification. The performance between the control chips usually decreases. As the device integration increases, the control chips may be integrated to a single one chip and more functions are provided. For example, the CPU, north bridge and the south bridge are formed integrally into a single chip. Therefore, pins of the chip package become very important sources. In order to increase the speed of transactions between the control chips, a simplified and specific specification for use between the control chips is required.
SUMMARY OF THE INVENTION
The present invention provides a control chips, data transaction method between control chips within the control chipset and a bus arbitration method between the control chips within the control chipset. Therefore, the performance of the control chipset increases, and types and numbers of signal lines between the control chips are reduced.
The present invention provides a data transaction method of a control chipset and between control chips within the control chipset. The data or commands can be continuously transmitted without any waiting cycle, stop or retry.
The present invention a data transaction method of a control chipset and between control chips within the control chipset, wherein the signal lines for waiting status, data transaction cycle and stop/retry protocol are not required.
The present invention provides a bus arbitration method between control chips which can reduce the arbitration time.
The present invention provides a bus arbitration method between control chips which a bus grant signal line is not required.
According to the present invention, data buffers of the control chips of the control chipset have fixed size and amount. In addition, read/write acknowledge commands are asserted in sequence according to read/write commands, by which a control chips can detect the status of the buffers within another control chip. When a control chip asserts a command, the corresponding data must be prepared in advance. Th
Lai Jiin
Peng Sheng-Chang
Tsai Chau-Chad
Tsai Chi-Che
J. C. Patents
Mason Donna K.
Thai Xuan M.
Via Technologies Inc.
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