Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate
2000-03-14
2003-06-24
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
C713S500000, C713S502000, C711S100000, C711S101000, C711S105000
Reexamination Certificate
active
06584578
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates, in general, to the field of integrated circuit double data rate (“DDR”) dynamic random access memory (“DRAM”) devices. More particularly, the present invention relates to an arbitration method and circuit for control of DDR DRAM output first-in, first-out (“FIFO”) registers.
Historically, in order to synchronize data transfers among system logic devices, data transfers to/from conventional DRAM devices would be initiated on either the rising (the transition from logic level “zero” to “one”) or falling (the transition from logic level “one” to “zero”) edge of a clock signal. DDR DRAM memory devices differ from conventional DRAM by enabling output operations to occur on both the rising and falling edges of the clock, thereby effectively doubling the device's output frequency without increasing the actual clock frequency.
DDR DRAM device functionality is specified by a Joint Electron Devices Engineering Counsel (“JEDEC”) standard, one aspect of which is that the output data must be aligned with the input clock signal. One method utilized for DDR DRAM devices to be able to achieve this effective data alignment is by the inclusion of delay lock loop (“DLL”) circuitry to enable the pre-fetching of data sufficiently in advance of when it must be output. In general, this necessary advance is substantially constant for any given delays in the input/output (“I/O”) datapath. However, problems in device operation can sometime occur if the skew between the system and DLL clock signals exceeds an acceptable range.
SUMMARY OF THE INVENTION
Disclosed herein is an arbitration method and circuit for control of DDR DRAM device FIFO registers which allows the data path of the device to be functional over a wider range of system clock and DLL clock signal skews.
By comparing the system and DLL clocks, the circuit and method of the present invention determines whether the DLL clock should be considered “faster” than the system clock, or “slower.” Functionally, the circuit and method of the present invention attempts to force all cases into the “fast” condition until a determination is made that the amount of advance is now so fast that data corruption in the pipeline might occur. Only in this case will it force the result to be “slow,” adding 1 cycle to the output control path, and thereby correcting the data flow. In a particular embodiment disclosed herein, the overlaps (both clocks=1) of the DLL and system clock are compared against a predetermined limit. This predetermined limit, or delay, is based on knowledge of the entire data path and how much total advance in the DLL can be accurately supported.
Particularly disclosed herein is a method for associating a first clock signal with a second derivative clock signal and means for implementing the method comprising the steps of: determining an overlap between the first and second clock signals; comparing the determined overlap with a predetermined overlap limit; considering the second clock signal to be faster than the first clock signal if the determined overlap is less than the predetermined overlap limit; and utilizing the second clock signal to clock data through an integrated circuit device. In a particular embodiment the method and means for implementing the method may include the additional steps of alternatively considering the second clock signal to be slower than the first clock signal if the determined overlap is equal to or greater than the predetermined skew limit and adding one clock cycle delay to the data being clocked by the second clock signal.
Further disclosed herein is an arbitration circuit for an integrated circuit memory device data path that comprises a first portion coupled to receive a system clock signal, a second portion coupled to receive a delay locked loop clock signal and a third portion thereof coupled to receive a data sort clock signal derived from said system and delay locked loop clock signals. In a particular embodiment, the circuit is operative to mix system and delay locked loop data on the data path in accordance with a delay time between the system and delay locked loop clock signals.
Also further disclosed herein is a circuit for generating a data sort clock signal from an input system clock and delay locked loop clock signals. The circuit comprises first, second, third and fourth series connected switching devices, each having a respective control terminal thereof, with the delay locked loop clock signal being coupled to the control terminal of the first and fourth switching devices and the system clock signal being coupled to the control terminal of the second switching device. A delay circuit is coupled to receive the delay locked loop clock signal for providing a delayed delay locked loop clock signal to the control terminal of the third switching device and a latch circuit is coupled intermediate the first and second switching devices for providing the data sort clock signal.
REFERENCES:
patent: 6014341 (2000-01-01), Koshikawa
patent: 6242960 (2001-06-01), Bae
patent: 6249483 (2001-06-01), Kim
patent: 6369615 (2002-04-01), Shimizu et al.
Hogan & Hartson LLP
Kubida William J.
Lee Thomas
Meza Peter J.
Mosel Vitelic Inc.
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