Arbitrating access for a plurality of data channel inputs...

Details Arbitrating access for a plurality of data channel inputs... Arbitrating access for a plurality of data channel inputs...

2004-10-21

2009-11-03

Patel, Niketa I (Department: 2181)

Electrical computers and digital data processing systems: input/

Input/output data processing

Peripheral adapting

C370S461000, C370S462000

Reexamination Certificate

active

07613856

ABSTRACT:
A configurable buffer arbiter is provided that combines a time-slot based algorithm, a fairness-based algorithm, and a priority-based algorithm to meet the bandwidth and latency requirements of multiple channels needing access to a buffer memory. The channels have different static and dynamic characteristics. The static channel characteristics include aspects such as a required latency for access to the buffer memory, a required bandwidth to the buffer memory, a preferred latency or bandwidth to the buffer memory, the amount of data the channel can burst in each access to the buffer memory, and the ability for the channel to continuously burst its data to the buffer memory with or without any pauses. The dynamic characteristics include aspects such as whether a channel's FIFO is nearing full or empty, or whether one of the static characteristics has suddenly become more critical. Configuration of the arbiter algorithms exists to optimize the arbiter for both the static and dynamic channel characteristics.

REFERENCES:
patent: 5913045 (1999-06-01), Gillespie et al.
patent: 6584531 (2003-06-01), Singh
patent: 2004/0006659 (2004-01-01), Lee
patent: 2005/0223131 (2005-10-01), Goekjian et al.
Dave Pahl, Maximizing Data Transfer Efficiency with C5000 DMA Controller, Sep. 12, 2001 ,Texas Instuments, pp. 1- 58.

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