Arbiters with preferential enables for asynchronous circuits

Details Arbiters with preferential enables for asynchronous circuits Arbiters with preferential enables for asynchronous circuits

2006-06-20

2006-06-20

Le, Don (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

C326S093000, C326S052000, C710S240000

Reexamination Certificate

active

07064583

ABSTRACT:
One embodiment of the present invention provides a circuit that preferentially grants requests. This circuit monitors at least two inputs for request signals and at least two inputs for enable signals, wherein each request signal is associated with a corresponding enable signal. If any enable signal is asserted and only one request signal is asserted, the circuit asserts a grant signal associated with the asserted request signal. Otherwise, if a single enable signal is asserted and multiple request signals are asserted, the circuit preferentially asserts the grant signal of the request signal associated with the asserted enable signal.

REFERENCES:
patent: 4864243 (1989-09-01), Reese
patent: 5341052 (1994-08-01), Dike et al.
patent: 5713025 (1998-01-01), Molnar et al.
patent: 2004/0156323 (2004-08-01), Cao
patent: 2004/0243752 (2004-12-01), O'Connor et al.

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