Arbiter for queue management system for allocating bus...

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation

Reexamination Certificate

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Details

C710S117000, C710S107000, C710S244000, C710S052000, C710S310000, C710S045000, C710S309000

Reexamination Certificate

active

06898649

ABSTRACT:
An arbiter (7) is provided for a QMS having multiple queue users (5A to5D), each having real time requirements for mastership of a bus (31). The arbiter (7) is arranged so that the amount of time that each queue user (5A to5D) can gain bus access is a percentage of the total bus time.

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