Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1995-06-02
2002-04-23
Nguyen, Ha Tran (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S592000, C438S659000, C438S660000, C438S664000, C438S683000, C438S684000, C438S745000
Reexamination Certificate
active
06376372
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to semiconductor processing and more specifically to silicide formation on narrow polysilicon lines.
BACKGROUND OF THE INVENTION
A typical silicide process consists of three steps: a silicide react step, a TiN (titanium nitride) strip, and a silicide anneal. During the react step, a refractory metal (e.g., titanium) is reacted in a N
2
(nitrogen) ambient to form silicide where the titanium reacts with silicon, and forms TiN elsewhere. The silicide formed during the react step is typically present as the higher resistivity phase known as C49. The TiN strip step removes the TiN layer formed during the react step. The anneal step is then used to transform the high silicide resistivity C49 phase into a lower silicide resistivity phase known as C54.
Silicide cladding of the polysilicon gate and the source/drain regions in VLSI (very large scale integrated) circuits using titanium silicide is a popular approach for reducing the transistor series resistance and local interconnect delays in VLSI circuits. The sheet resistance of heavily doped, silicided polysilicon lines is known to be a function of linewidth, particularly for sub-micron linewidths. One explanation for this is that a lower percentage of the silicide transforms from the higher resistivity C49 phase to the lower resistivity C54 phase on sub-0.5 &mgr;m polysilicon lines. Current sheet resistances for linewidths under 0.5 &mgr;m are particularly problematic. Hence, there is a need to alleviate this problem and reduce the dependence of the silicide sheet resistance on linewidth.
Several methods have been used to reduce the silicide sheet resistance. One method of reducing the silicide sheet resistance is to increase the temperature of the anneal. However, higher temperature leads to agglomeration of the silicide. Higher temperature also leads to lateral overgrowth of the silicide which is unacceptable for self-aligned silicide processing. Lateral overgrowth results in undesirable conductive silicide stringers between the polysilicon gate and the source/drain region of MOS transistors. Therefore, only minimal advances may be made by increasing temperature.
Another approach is to use a pre-react amorphization implant either prior to the titanium deposition or just after it, but in either case, before the silicide react step. This implant breaks the bonds of the polysilicon. The broken bonds yield an increased number of reaction sites for the silicide react and enhance the diffusion of silicon toward the growing silicide. This accelerates the silicide formation and thus reduces the silicide sheet resistance. However, even further reduction in silicide sheet resistance is needed.
SUMMARY OF THE INVENTION
A silicide process using a pre-anneal amorphization implant prior to silicide anneal is disclosed herein. A layer of titanium is deposited and reacted to form titanium silicide and titanium nitride. The titanium nitride is removed and a pre-anneal amorphization implant is performed to enable increased transformation of the silicide from a higher resistivity phase to a lower resistivity phase. After the implant, the silicide anneal is performed to accomplish to transformation. An advantage of the invention is providing a silicide process having reduced silicide sheet resistance for narrow polysilicon lines.
REFERENCES:
patent: 4835112 (1989-05-01), Pfiester et al.
patent: 4877748 (1989-10-01), Havemann
patent: 5346836 (1994-09-01), Manning et al.
patent: 5401674 (1995-03-01), Anjum et al.
patent: 5470794 (1995-11-01), Anjum et al.
patent: 5508212 (1996-04-01), Wang et al.
S. Wolf “Silicon Processing for the VLSI Era, vol. 2”, Lattice Press, 1990, pp. 144-148.
Apte Pushkar Prabhakar
Moslehi Mehrdad M.
Paranjpe Ajit Pramod
Brady W. James
Hoel Carlton H.
Nguyen Ha Tran
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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