Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Reexamination Certificate
2000-10-23
2001-05-29
Mai, Son (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including level shift or pull-up circuit
C365S189090, C365S185180, C327S333000, C326S080000, C326S081000
Reexamination Certificate
active
06240027
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
This invention relates to semiconductor memories, in particular flash memories and providing voltages for erase operations.
2. Description of Related Art
In conventional flash memories both a high negative and a high positive voltage are required to erase data in flash memory cells. The high negative voltage is applied to the gate of the flash cell being erased and the high positive voltage is applied to the source. The drain is usually left floating. This requires that both a positive pump circuit and a negative pump circuit exist on the flash memory chip if the flash memory cells are to be erased after assembly. There are several problems that must be handled when two pump circuits of opposite polarity are on the same chip. Besides increase in chip power, considerable protection circuitry and guarding methodology are required to isolate the pump circuitry and avoid device breakdown.
Using internal pump circuits to perform erasure of flash memory cells is a somewhat slow process since it takes time for the pump circuits to get to the required voltage after being activated. For this reason it is advantageous to programming and erasure during manufacture to provide high negative and high positive voltages to chip pads from external to the chip, thus speeding up the programming process. In the manufacture of flash memory cells providing an external high positive voltage has been known for some time; however, because of the difficulties of handling a high negative voltage, external supplied high negative voltages have not been previously used. By providing an externally applied high negative voltage along with an externally applied high positive voltage to a chip containing a flash memory shorter erase/program, lower power consumption and faster throughput can be realized.
SUMMARY OF THE INVENTION
In this invention a method and circuitry are disclosed that allow a high negative voltage and a high positive voltage to be applied to flash memory cells being erased from external to the chip containing the flash memory cells with or without high negative voltage and high positive voltage pump circuits. The high negative voltage and the high positive voltage are connected to the chip through chip pads and are used during manufacture to erase and program the chip. If erasure and programming of flash memory cells is not required after assembly the high positive and high negative voltage pump circuits are not implemented on the chip, and the high voltage and high positive voltage chip pads are the only source of voltages for flash memory cell erasure.
If the chip containing flash memory cells has high negative and high positive voltage pump circuits, the chips can be erased/programmed by a user after assembly. In this case the external high negative and high positive voltages are connected in parallel to the output of the corresponding pump circuits, and the pump circuits are controlled off when the external high voltages are to be used. The external high voltages are used before assembly during manufacture to shorten erase/ program time, lower power consumption and increase manufacturing throughput. After assembly no external voltages are connected to the high negative and high positive voltage pads, and the internal pump circuits must be used if the flash memory cells are to be erased/programmed by a user.
A high negative voltage level shifter circuit using NMOS transistors in a P-well inside a deep N-well on a P-substrate provides select and deselect bias for gates of flash memory cells. To avoid forward biasing P-N junctions when a high negative voltage is applied to a gate of a cell being erased, a triple well comprising a P-well inside a deep N-well on a P-substrate is used for the NMOS transistors. The negative voltage level shifter circuit provides a high negative voltage to the gate of a flash memory cell being erased and a moderate positive voltage to the gate of a cell not being erased.
The high negative voltage level shifter forms a part of a voltage control module located on the chip containing a flash memory. Control signals connected to the control module provide commands that direct the output state of the high negative voltage level shifter between a high negative voltage to select flash memory cells for erasure and a moderate positive voltage to deselect the flash memory cells from erasure. The level shifter comprises a cross coupled pair of N-channel transistors that provide two operating states. A voltage selector circuit comprising two P-channel transistors is connected to the cross coupled pair of N-channel transistors through a bias buffer circuit to select one of the two operating states. The voltage selector circuit is switched between two input voltages which switches the cross coupled pair of N-channel transistors between two states and drives the differential circuit to switch between a high negative voltage to select the gate of a flash memory cell for erasure and a moderate positive voltage that deselects the gate of a flash memory cell from the erase operation.
Similar to the high negative voltage level shifter, a high positive voltage level shifter provides a high positive voltage to the source of a flash memory cell being erased and a moderate positive voltage to the source of a flash memory cell being deselected from the erase operation. The high positive voltage level shifter circuit uses PMOS transistors in an N-weEl on a P-substrate and provides select and deselect bias for sources of flash memory cells. To avoid forward biasing P/N junctions when a high positive voltage is applied to a gate of a cell being erased the P-channel transistors are contained in an N-well. The positive voltage level shifter circuit provides a high positive voltage to the source of a flash memory cell being erased and a moderate positive voltage to the source of a cell not being erased.
The high positive voltage level shifter forms a part of a voltage control module located on the chip containing a flash memory. Control signals connected to the control module provide commands that direct the output state of the high positive voltage level shifter between a high positive voltage to select flash memory cells for erasure and a moderate positive voltage to deselect the flash memory cells from erasure. The level shifter comprises a cross coupled pair of P-channel transistors that provide two operating states. A voltage selector circuit comprising two N-channel transistors is connected to the cross coupled pair of P-channel transistors through a bias buffer circuit to select one of the two operating states. The voltage selector circuit is switched between two input voltages which switches the cross coupled pair of P-channel transistors between two states and drives the differential circuit to switch between a high positive voltage to select the source of a flash memory cell for erasure and a moderate positive voltage that deselects the source of a flash memory cell from the erase operation.
It is possible to provide the erase function for flash memory cells with only one voltage requiring a pump circuit or an external chip pad. This can be done through voltage rotation by adding a negative voltage to the high positive gate erase voltage so that the source erase voltage becomes the chip positive bias voltage. Then adding this same negative voltage to the high negative gate voltage and to the semiconductor bulk with the drain remaining floating. This voltage rotation eliminates the need for the high positive source voltage and in turn eliminates the need for the high positive voltage pump circuit.
REFERENCES:
patent: 5821800 (1998-10-01), Le et al.
patent: 6041014 (2000-03-01), Atsumi et al.
patent: 6101126 (2000-08-01), Chung et al.
patent: 6166968 (2000-12-01), Song
Chen Mike Hsinyih
Hsu Fu-Chang
Lee Peter Wung
Ackerman Stephen B.
Aplus Flash Technology Inc.
Mai Son
Saile George O.
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