Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-06-20
2006-06-20
Thompson, A. M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07065729
ABSTRACT:
A computer-implemented approach for routing an integrated circuit using non-orthogonal routing is accomplished during two phases: a global routing phase and a detailed routing phase. During global routing, routing indicators, in the form of hint polygons, are added to the integrated circuit layout and strategy lists, that include bias directions and straying limits, are generated for the new wires to be added. The hint polygons and strategy lists are used during detailed routing to aid in placing the new wires. If obstacle conflicts or insufficient space problems prevent the detailed routing of a new wire, then an obstacle resolution portion of global routing is used to resolve the obstacle conflict and/or provide additional space in the integrated circuit layout to route the new wires. Obstacle resolution includes, without limitation, moving or changing layout geometry, changing or add hint polygons, changing the routing strategy by changing the bias direction and/or adjusting straying limits, inserting one or more layer changes, instructing the detailed router to backup and insert a bend, ripping-up and rerouting one or more wires, or routing the wire from the destination connection point. Also, a tight routing approach may be employed to accommodate constructing routing paths in tight layout areas. Object specific design rule checks are employed to increase routing flexibility optimize routing performance. “On-the-fly” design rule checks are performed on portions of routing paths as the routing paths are being constructed.
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Becker Edward A.
Hickman Palermo Troung & Becker LLP
Thompson A. M.
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