Electrical computers and digital data processing systems: input/ – Interrupt processing – Processor status
Reexamination Certificate
2005-08-22
2009-08-25
Cleary, Thomas J (Department: 2111)
Electrical computers and digital data processing systems: input/
Interrupt processing
Processor status
C710S260000, C718S105000
Reexamination Certificate
active
07581052
ABSTRACT:
A method and apparatus for distributing multiple interrupts among multiple processors is disclosed. According to one embodiment, an interrupt daemon monitors the interrupt load among the processors that results from an initial mapping of the interrupts to the processors. The interrupt daemon determines whether there is a sufficient imbalance of the interrupts among the processors. If so, the interrupt daemon triggers a reassignment routine that generates a new mapping of the interrupts among the processors, and if not, the interrupt daemon goes to sleep for a specified time period. If the new mapping produces a sufficient improvement in the distribution of interrupts among the processors, based on the same criteria used to detect the imbalance, the new mapping is used by the central hub for subsequent distribution of interrupts to the processors. However, if the new mapping does not provide a sufficient improvement, the original mapping continues to be used.
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Cleary Thomas J
Osha • Liang LLP
Sun Microsystems Inc.
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