Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-05-01
2002-11-12
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06480990
ABSTRACT:
THE FIELD OF THE INVENTION
The present invention relates to application specific integrated circuits (ASIC). More particularly, it relates to an ASIC, especially a multiple metal layer ASIC, having easily accessible spare gate wiring.
BACKGROUND OF THE INVENTION
An application specific integrated circuit (ASIC) is a microelectronic integrated circuit chip designed specifically for an application or product, such as a computer system. The ASIC forms, in a single, semi-conductor substrate, the equivalent of several different integrated circuits each designed to perform one or more desired operations, such as a microprocessor operation, a memory operation, various interface operations (e.g., memory interface, processor interface), etc. Effectively, then, the ASIC is definable by one or more operational zones or “blocks” each having desired operational capabilities.
ASIC operational blocks are typically designed to include thousands of individual logic gates necessary for performing the desired operation(s). These logic gates (or “operational logic gates”) are formed in a substrate layer according to known semi-conductor fabrication techniques. The operational logic gates can assume a wide variety of forms, and include varying circuitry configurations. Once formed, the various operational logic gates are subsequently interconnected by wiring routed into metal layer(s) formed on top of the substrate. So as to optimize operational block size, the various operational logic gates associated with a particular operational block are located in relative close proximity to one another. By densely packaging the operational logic gates, the length of the interconnecting wiring including individual wiring “runs”, is minimized. In accordance with this general design concept, all of the operational logic gates of a particular block are formed within a relatively small area, thereby defining a boundary within which all of the operational logic gates are located. The boundary associated with a particular operational block does not physically appear on the chip, but instead exists in the abstract.
While every effort is made to properly design and configure the ASIC and each individual operational block, invariably performance problems may arise. For example, the operational block may not perform desired operation(s), logic “bugs” may be identified, logic changes required, one or more of the logic gates or wiring may be defective, etc. Rather than scrap the entire chip, repairs are typically performed to correct the identified problem. A widely employed technique for facilitating ASIC repair is to randomly dispense a number of spare logic gates throughout the operational block. A variety of different logic gates, such as AND gates, OR gates, NAND gates, NOR gates, invertors, flip-flops, and registers, are typically provided. The spare logic gates are, similar to the operational logic gates, wired to one another via the metal layer(s). By providing the operational block layout with the spare logic gates, when logic changes are required or desired, one or more the spare logic gates able to correct the problem can be identified and incorporated into the operational logic gate circuitry. As there are already wires between the spare logic gates, it is likely that there will be points along those wires from which the desired spare logic gate(s) can be wired into the functional chip logic.
One readily available technology useful for forming the above-described repair wiring is referred to as focused ion beam (FIB). The FIB technique can be used as an aide in integrated circuit design and debug by performing rapid device alteration. A beam of Ga ions is focused and scanned over the surface of the chip. The interaction of the ion beam with the sample results-in ejection of atoms from the surface (sputtering) is used to expose buried wiring lines for eventually cutting/attaching to other circuit elements. The holes and cuts can be very accurately placed (within about 0.1 &mgr;m) and can reach buried layers. Conversely, FIB can be implemented to deposit a metal layer or wire when performed in the presence of an organometallic gas. This formed metal layer or wire, in turn, can be used to make connections from one device to another.
While the FIB repair technique is highly viable, certain limitations have been identified. In particular, ASIC technology has evolved to require the use of multiple metal layers over the semi-conductor substrate layer. For example, current chip designs incorporate six metal layers. The wiring connecting the various operational logic gates, as well as the spare logic gates, is formed along one or more of these metal layers. Typically, an automatic routing tool determines and routes individual wires as each successive metal layer is formed. Statistically speaking, it is highly likely that the automatic routing tool will route or place the interconnecting wire for closely positioned logic gates along one of the inner most metal layers. Thus, with randomly dispersed spare logic gates, it is impossible to ensure that the associated interconnecting wiring will extend to one of the outer most metal layers; instead, the automatic routing tool will “optimize” wire location to one of the inner most metal layers. While the operational block density is therefore also optimized, the ability to effectuate FIB repairs may be greatly impeded. In general terms, the FIB can access wiring located on the outer most metal layer, as well as the metal layer directly beneath the outer most layer. In addition, FIB may be able to access intermediate metal layers. However, the FIB cannot reach inner metal layers, such as those formed beneath four or more metal layers. In short, FIB technology can only reach wires in the top few metal layers of an ASIC. Where six or more metal layers are employed, spare logic gates connected by wiring formed on the inner most metal layers are essentially useless as the wiring is not accessible by FIB.
Integrated circuit technology continues to evolve and improve. The complexity of ASIC designs has increased exponentially, as well as the fabrication of these chips. In this regard, the availability of spare logic gates to address unforeseen logic/performance problems remains a necessity. However, currently employed ASIC operational block design techniques may render the spare logic gates unusable, especially for multiple metal layer designs. Therefore, a need exists for an ASIC operational block design including spare logic gates strategically located to ensure accessibility by a repair tool, and a method for ensuring this desired configuration. The resulting ASIC would be highly useful for a number of devices, including computer systems.
SUMMARY OF THE INVENTION
One aspect of the present invention provides an application specific integrated circuit. The ASIC includes a substrate layer, at least one metal layer and an operational block. The metal layer is formed above the substrate layer. The operational block is formed in the substrate layer and the metal layer, and is definable by a two-dimensional boundary. With this in mind, the operational block includes a plurality of operational logic gates, a first subgroup of spare logic gates, a second subgroup of spare logic gates, operational wiring and spare gate wiring. The operational logic gates and the spare logic gates are formed in the substrate layer, positioned within the boundary. Further, the first subgroup is spaced from the second subgroup. The operational wiring is formed in the metal layer and interconnects the operational logic gates to configure the operational block to perform a desired operation. Finally, the spare gate wiring is formed in the metal layer. In this regard, the spare gate wiring is separate from the operational wiring, and connects at least one of the first subgroup spare gates to at least one of the second subgroup spare logic gates. In one preferred embodiment, the operational block boundary defines a major dimension, and a spacing between the first and second subgroups is at least one-half the ma
Sharp Nolan David
Yu Henry C.
Do Thuan
Smith Matthew
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