Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2000-09-25
2003-09-23
Thai, Xuan M. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S100000, C714S100000
Reexamination Certificate
active
06625684
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to application specific integrated circuits particularly though not necessarily exclusively intended to constitute the data handling and switching requirements of a network device intended for use in a packet-based communication system or as a modular part of such a device. The invention more particularly relates generally to the reading and to writing of data in to and out of registers within the application specific integrated circuit and the monitoring of data available on visibility buses within the circuit.
BACKGROUND TO THE INVENTION
Application specific integrated circuits, both in the specific context indicated above and more generally, commonly contain a multiplicity of registers for the storage of data, which may be message data or control data. It is also common place to provide an addressable multiplexing and demultiplexing system which is addressable by means of, for example, a central processing unit so that data may be written in to or read out of such registers. Broadly, each operational ‘block’ within the ASIC may have data buses which are addressable by part of an address supplied by a CPU and the data buses each common to a particular operating block may be selectable by a further multiplexing or demultiplexing stage by other parts of an address supplied by a CPU so that a selected data bus may supply data to or receive data from a bi-directional buffer for the ASIC. Address data may be supplied to appropriate externally accessible pins of the ASIC and the bidirectional buffer may also be associated with a set of pins by means of which data may be written in to or read out of the buffer as the case may be.
It is also commonplace for ASICs to include other data buses known as ‘visibility’ buses which are provided for each operational block and which provide data denoting the operational state of appropriate parts of the block. Such visibility buses are intended only for monitoring preferably in real time, and provide normally multi-bit data outputs denoting, for example, the state of a respective register in a state machine within the respective block.
A broad difference between data buses and visibility buses is that data on the former should be temporarily stored (in a register) until a reading cycle is completed, whereas data on the latter needs to be viewed in real time without storage or clocking.
It is usual for visibility buses to be brought out, with the aid of a multiplexing system if appropriate, to dedicated pins of the ASIC.
It is the general object of the invention to reduce the need for visibility buses other than within operational blocks of the ASIC and more particularly to render unnecessary the provision of externally accessible pins coupled to such visibility buses.
SUMMARY OF THE INVENTION
The present invention is based on the use of a common multiplexing system for read out of data both on data buses and visibility buses. In a preferred form, the invention employs a common multiplex system for data and visibility buses within each block and with an interface blocks by means of which data may be read out either from the data buses or validity buses to a common buffer which is externally accessible, for example by an external CPU.
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Allwright Gareth E
Casey Fergus
Choi Kam
Gavin Vincent
Gibson Patrick
3Com Corporation
Thai Xuan M.
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