Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2000-06-29
2003-10-07
Thai, Xuan M. (Department: 2189)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S013000, C710S035000, C710S300000, C370S410000, C370S412000, C370S446000
Reexamination Certificate
active
06631435
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of providing an interface for applications to communicate over a bus structure. More particularly, the present invention relates to the field of controlling bus management and data transfer operations between applications over a bus structure in both asynchronous and isochronous formats.
BACKGROUND OF THE INVENTION
The IEEE 1394-1995 standard, “1394 Standard For A High Performance Serial Bus,” is an international standard for implementing an inexpensive high-speed serial bus architecture which supports both asynchronous and isochronous format data transfers. Isochronous data transfers are real-time transfers which take place such that the time intervals between significant instances have the same duration at both the transmitting and receiving applications. Each packet of data transferred isochronously is transferred in its own time period. An example of an ideal application for the transfer of data isochronously would be from a video recorder to a television set. The video recorder records images and sounds and saves the data in discrete chunks or packets. The video recorder then transfers each packet, representing the image and sound recorded over a limited time period, during that time period, for display by the television set. The IEEE 1394 standard bus architecture provides multiple channels for isochronous data transfer between applications. A six bit channel number is broadcast with the data to ensure reception by the appropriate application. This allows multiple applications to simultaneously transmit isochronous data across the bus structure. Asynchronous transfers are traditional data transfer operations which take place as soon as possible and transfer an amount of data from a source to a destination.
The IEEE 1394 standard provides a high-speed serial bus for interconnecting digital devices thereby providing a universal I/O connection. The IEEE 1394 standard defines a digital interface for the applications thereby eliminating the need for an application to convert digital data to analog data before it is transmitted across the bus. Correspondingly, a receiving application will receive digital data from the bus, not analog data, and will therefore not be required to convert analog data to digital data. The cable required by the IEEE 1394 standard is very thin in size compared to other bulkier cables used to connect such devices. Devices can be added and removed from an IEEE 1394 bus while the bus is active. If a device is so added or removed the bus will then automatically reconfigure itself for transmitting data between the then existing nodes. A node is considered a logical entity with a unique address on the bus structure. Each node provides an identification ROM, a standardized set of control registers and its own address space.
The IEEE 1394 standard defines a protocol as illustrated in FIG.
1
. This protocol includes a serial bus management block
10
coupled to a transaction layer
12
, a link layer
14
and a physical layer
16
. The physical layer
16
provides the electrical and mechanical connection between a device or application and the IEEE 1394 cable. The physical layer
16
also provides arbitration to ensure that all devices coupled to the IEEE 1394 bus have access to the bus as well as actual data transmission and reception. The link layer
14
provides data packet delivery service for both asynchronous and isochronous data packet transport. This supports both asynchronous data transport, using an acknowledgement protocol, and isochronous data transport, providing real-time guaranteed bandwidth protocol for just-in-time data delivery. The transaction layer
12
supports the commands necessary to complete asynchronous data transfers, including read, write and lock. The serial bus management block
10
contains an isochronous resource manager for managing isochronous data transfers. The serial bus management block
10
also provides overall configuration control of the serial bus in the form of optimizing arbitration timing, guarantee of adequate electrical power for all devices on the bus, assignment of the cycle master, assignment of isochronous channel and bandwidth resources and basic notification of errors.
An application programming interface (API) for applications using the IEEE 1394 standard serial bus has been developed by Skipstone for enabling the application to use the IEEE 1394 bus for data transfers. With their API, Skipstone includes a manual entitled “The SerialSoft IEEE 1394 Developer Toolkit,” available from Skipstone, Inc., 3925 West Braker Lane, #425, Austin, Tex. 78759. Skipstone defines their API as a collection of programming calls to be used by the application to manage data being written to and obtained from a device over an IEEE 1394 bus. To initialize an isochronous transfer, several asynchronous data transfers may be required to configure the applications and to determine the specific channel which will be used for transmission of the data. Once the channel has been determined, buffers are used at the transmitting application to store the data before it is sent and at the receiving application to store the data before it is processed. In a transmitting application, the Skipstone API actively manages the transfer of data from the appropriate portion of the appropriate buffer onto the bus structure, during the appropriate time period. In a receiving application, the Skipstone API actively manages the reception of data from the bus structure, storing the data in the appropriate portion of the appropriate buffer and the processing of the data in the appropriate time period.
During asynchronous data transfers, the Skipstone API actively manages the required transactions to complete the data transfer. During an asynchronous incoming write transaction, the application provides a buffer to the API, mapped to a certain area of the 1394 bus address space. As write transactions arrive at the API, their data is written to the buffer. During an asynchronous incoming read transaction the application is responsible for making sure that the buffer contains useful information. The 1394 bus driver then reads the data from the buffer at the requested address when the read transaction arrives. For both write and read transactions, the Skipstone API actively manages and generates each necessary transaction. For example, if a block of data is being transferred to the application, of a size requiring multiple transactions, the Skipstone API requires the application to describe each 1394 transaction necessary to complete the transfer of the block of data. This consumes significant overhead by the processor of the application as well as the full attention of the API during an asynchronous data transfer operation.
The Skipstone API supports isochronous data transfer operations in a similar way. Specifically, the application must describe each isochronous packet to the Skipstone API. The Skipstone API then transmits each packet at the proper time. This requires significant processor overhead and thereby prohibits efficient processing of the isochronous data by the application.
A block diagram of an exemplary IEEE 1394-1995 serial bus network including a computer system and a video camera is illustrated in FIG.
7
. The computer system
200
includes an associated display
202
and is coupled to the video camera
204
by the IEEE 1394-1995 serial bus cable
206
. Video data and associated data are sent between the video camera
204
and the computer
200
over the IEEE 1394-1995 serial bus cable
206
.
A block diagram of the internal components of the computer system
200
is illustrated in FIG.
8
. The computer system
200
includes a central processor unit (CPU)
244
, a main memory
230
, a video memory
246
, a mass storage device
232
and an IEEE 1394-1995 interface circuit
228
, all coupled together by a conventional bidirectional system bus
234
. The interface circuit
228
includes the physical interface circuit
242
for sending and receiving communications on the IE
Fairman Bruce A.
Lym Kevin K.
Shima Hisato
Smyers Scott
Haverstock & Owens LLP
Sony Corporation
Thai Xuan M.
Vo Tim
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