Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-10-03
2006-10-03
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C703S016000, C703S002000
Reexamination Certificate
active
07117465
ABSTRACT:
A method for facilitating the sequential verification of loop-free circuits by reducing the sequential verification problem to combinational verification, by constructing and comparing Timed Binary Decision. Diagrams (TBDDs) and Timed Binary Expression Diagrams (TBEDs). The TBEDs can be compared by using both BDDs and SAT solvers.
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Hanna Ziyad
Khasidashvili Zurab
Moondanos John
Fleshner & Kim LLP
Intel Corporation
Kik Phallaka
LandOfFree
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