Application of gate edge liner to maintain gate length CD in...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having schottky gate

Reexamination Certificate

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C438S184000, C438S197000, C257SE21409, C257SE21444

Reexamination Certificate

active

10916322

ABSTRACT:
A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selective to wet chemicals used to remove the dummy gate oxide thereby preventing undercut in the spacer region. The method is aimed at making the metal gate electrode technology a feasible technology with maximum compatibility with the existing fabrication environment for multiple generations of CMOS transistors, including those belonging to the 65 nm, 45 nm and 25 nm technology nodes, that are being used in analog, digital or mixed signal integrated circuit for various applications such as communication, entertainment, education and security products.

REFERENCES:
patent: 6559051 (2003-05-01), Buynoski et al.
patent: 2001/0023108 (2001-09-01), Miyano et al.
patent: 2004/0029345 (2004-02-01), Deleonibus et al.
patent: 2005/0148130 (2005-07-01), Doczy et al.
Guillaumot, B. et al., “75nm Damascene Metal Gate and High-k Integration for Advanced CMOS Devices”, 2002.
Yagishita, Atsushi et al., “High Performance Damascene Metal Gate MOSFEpT's for 0.1 μm Regime”, IEEE Transactions on Electron Devices, vol. 47, No. 5, May 2000.
Tavel, B. et al., “High Performance 40 nm nMOSFETs With HfO2 Gate Dielectric and Polysilicon Damascene Gate”, 2002.
Matsuo, Kouji et al., “High Performance Damascene Gate CMOSFETs with Recessed Channel Formed by Plasma Oxidation and Etching Method (RC-POEM)”, 2002.

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