Application of deep-junction non-self-aligned transistors for su

Details Application of deep-junction non-self-aligned transistors for su Application of deep-junction non-self-aligned transistors for su

1987-09-16

1989-06-13

James, Andrew J.

357 239, 357 234, 357 20, H01L 2978, H01L 2906

Patent

active

048397040

ABSTRACT:
A structure and method of fabricating same is provided for a deep junction, non-self-aligned MOS transistor for suppressing hot carrier injection. According to the invention, dopant is introduced into a semiconductor substrate of a first conductivity type to form first and second spaced-apart substrate regions of opposite conductivity in the substrate. The first and second regions will become the source and drain regions of a deep junction, non-self-aligned MOS transistor having an effective channel length less than about 3.5 microns. The junction depth of the source and drain regions is greater than about 4000 Angstroms. Next, a layer of dielectric material is formed over the substrate. A region of conductive material is then formed over the dielectric material to serve as the gate of the MOS device. The resulting deep junction device has improved reliability as compared to self-aligned MOS devices of comparable effective channel length.

REFERENCES:
patent: T954008 (1977-01-01), Baitinger et al.
patent: 4532698 (1985-08-01), Fang et al.
patent: 4729001 (1988-03-01), Haskell

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