Apparatuses configured to engage a conductive pad

Details Apparatuses configured to engage a conductive pad Apparatuses configured to engage a conductive pad

2006-08-29

2006-08-29

Coleman, W. David (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Test or calibration structure

C324S754090

Reexamination Certificate

active

07098475

ABSTRACT:
A method of engaging electrically conductive test pads on a semiconductor substrate having integrated circuitry for operability testing thereof includes: a) providing an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate; b) engaging the grouping of apexes with the single test pad on the semiconductor substrate; and c) sending an electric signal between the grouping of apexes and test pad to evaluate operability of integrated circuitry on the semiconductor substrate. Constructions and methods are disclosed for forming testing apparatus comprising an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate.

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Moto'o Nakano, “A Probe for Testing Semiconductor Integrated Circuits and a Test Method Using Said Probe”, Mar. 25, 1991, Japanese Patent Office Disclosure No. Hei 3-69131, Filing No. Hei 1-205301, filing date Aug. 8, 1989.

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