Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2007-08-14
2007-08-14
Chang, Daniel (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S121000, C365S203000, C327S544000
Reexamination Certificate
active
11099186
ABSTRACT:
A method and apparatus for shifting a dynamic circuit, driven by a one-shot clock, to a pre-charge mode, during a power-off mode, is provided. Under certain conditions, a floating node may be present in a dynamic circuit. One approach to prevent floating nodes involves the generation of a new one-shot clock signal that is supplied to the last dynamic circuit in the series of dynamic circuits before the output flop (“the final dynamic circuit”). The new one-shot clock signal is driven to a logical low value when the power-off signal has a logical high value. Another approach to prevent floating nodes involves modifying the final dynamic circuit to include a structure that, when the power-off signal has a logical high value, drives the dynamic node to either a logical high value or a logical low value to prevent the dynamic node from becoming a floating node.
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patent: 6429689 (2002-08-01), Allen et al.
patent: 6873188 (2005-03-01), Belluomini et al.
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Im Yonghee
Kim Han Bin
Lee Kyung T.
Brokaw Christopher J.
Chang Daniel
Hickman Palermo Truong & Becker
Sun Microsystems Inc.
Truong Bobby K.
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