Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2005-11-29
2005-11-29
Peikari, B. James (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S208000, C711S207000, C711S206000, C711S202000, C711S203000, C711S205000, C711S221000, C711S170000, C711S171000, C711S172000, C711S173000
Reexamination Certificate
active
06970992
ABSTRACT:
A data processing system includes at least one system processor, chipset core logic, main memory to store computer software and data including operating system software, and a graphics address remapping table (GART). The chipset logic operates on first-sized real memory pages, while the operating system operates on larger, second-sized virtual memory pages. In an embodiment GART driver software maps each virtual page to Z continuous or non-contiguous real pages by filling up the GART with Z entries per virtual page, where Z is the rounded integer number of first-sized pages per second-sized page. In another embodiment, an address translation function converts a target address, corresponding to an address within a virtual page, issuing from a processor into a second address, corresponding to a base address of a real page in main memory. Also described are an integrated circuit and a computer-readable medium to map memory pages of disparate sizes.
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Gurumoorthy Nagasubramanian
Sadashivaiah Shivaprasad
Intel Corporation
Peikari B. James
Schwegman Lundberg Woessner & Kluth P.A.
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