Apparatus to guarantee TLB inclusion for store operations

Details Apparatus to guarantee TLB inclusion for store operations Apparatus to guarantee TLB inclusion for store operations

1996-06-07

1999-07-27

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

395392, G06F 1210

Patent

active

059308320

ABSTRACT:
A computer system includes a processor and a cache and memory management unit. The processor includes a means for retiring instructions in program order. The cache and memory management unit includes means for detecting when a translation has been evicted from a lookaside buffer and means for communicating eviction information to the means for retiring instructions in program order. The means for retiring instructions in program order includes means for holding a storage related instruction which causes a miss in the lookaside buffer or in the cache in a first pass of execution until the instruction becomes the oldest storage related instruction in program sequence and further includes means responsive to the eviction information for flushing all storage related instructions except the current storage related instruction. The system avoids the occurrence of misses in the buffer late in execution (e.g., PASS 2 or later), thus avoiding a necessity for complex recovery provisions.

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IBM Technical Disclosure Bulletin, "Special Serialization for "Load-with-Update" Instruction to Reduce the Complexity of Register Renaming Circuitry", vol. 37, No. 10, Oct. 1994, pp. 59-60.

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