Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2002-04-08
2003-02-18
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S758000, C427S008000, C118S690000, C118S691000
Reexamination Certificate
active
06522009
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method and an apparatus for electroless plating, and more particularly, to a method and an apparatus for electroless plating of a metal layer in the manufacture of an integrated circuit device.
(2) Description of the Prior Art
Electroless plating is an important process in the manufacture of integrated circuit devices. Electroless plating is used in the deposition of metal layers for interconnect levels and for input/out (I/O) pads.
Electroless plating may be defined as the deposition of a metal coating by immersion of a substrate in a suitable solution containing a chemical reducing agent. Metal ions in the solution are reduced by the chemical reducing agent and deposit on the substrate. Electroless plating resembles electroplating but is simpler and does not require an electric current. Due to the processing simplicity, electroless plating is particularly attractive for use in the fabrication of I/O pads with bumps.
Referring now to
FIG. 1
, a simplified, cross section of an electroless plating apparatus is shown. The basic components of the apparatus are the tank
10
and the wafer fixture
18
. The tank
10
may be a very simple container that holds the plating solution
14
and that does not react with the solution
14
. The wafer fixture
18
holds the semiconductor substrate
22
. The semiconductor substrate
22
is typically called a wafer. The wafer fixture
18
may hold a group of wafers, usually called a wafer lot or wafer batch. The wafer fixture
18
is constructed of a material that will not react with the plating solution
14
.
In a process run, the wafer
22
or wafer lot is loaded onto the wafer fixture
18
. The wafer fixture
22
indexes down to immerse the wafer
22
into the plating solution
14
. The plating solution typically contains many chemicals, including the plating metal ions and the reducing agent. The wafer fixture
18
may then move vertically and/or laterally to agitate the plating solution
14
and improve plating uniformity. The wafer fixture
18
suspends the wafer
22
in the solution for a predetermined period of time to plate a desired thickness of metal onto the semiconductor substrate surface. The wafer fixture
18
then indexes to the up position to remove the wafer
22
from the plating solution
14
. A rinsing operation may then be performed to remove any residual solution from the wafer
22
.
This simplified electroless plating apparatus of
FIG. 1
does not show many other features such as solution reservoirs, pumps, drains, motors, and controllers, that a state of the art apparatus would contain. However, for the purpose of explaining the concepts of the present invention, the simplified apparatus schematic is sufficient.
Note that ambient light
26
may penetrate into the plating solution
14
and strike the semiconductor substrate
22
. Light may enter the plating solution
14
through the opening at the top of the tank
10
. In addition, light may be transmitted through the sidewalls or the bottom of the tank
10
. In many applications of electroless plating, the presence of ambient light in the reaction is not a problem. However, for the case of a semiconductor substrate, this light can be detrimental to the plating process.
Referring now to
FIG. 2
, a cross section of an integrated circuit device is shown. This integrated circuit device has a substrate
30
comprising a semiconductor material such as monocrystalline silicon. In this example, the substrate
30
is lightly doped p-type. An n-type well
34
is also formed in the substrate
30
. A passivation layer
38
is formed overlying the surface of the substrate
30
. Openings have been formed in the passivation layer
38
for I/O pads. A first pad layer of aluminum
42
has been deposited in the pad openings.
The semiconductor substrate
30
is then submitted to the electroless plating process described in
FIG. 1
to plate a layer of nickel overlying the aluminum layer
42
. Ambient light
46
enters the plating solution as described above. A portion of this light
46
strikes the semiconductor substrate in the n-type well
34
.
Referring now to
FIG. 3
, an electron energy state diagram for the silicon substrate is shown. Electrons in the crystal silicon structure are in either the valence band or the conduction band. Electrons in the valence band have energy of or below E
valence
. Electrons in the conduction band have energy of or above E
conduction
. When electrons are in the valence band, they are held by the silicon atom. When electrons enter the conduction band, they have sufficient energy to leave the silicon atom and are then said to be available for conduction. A gap exists between the valence band and the conduction band. This gap is called the gap energy or E
gap
. When a light photon strikes the electron, energy is transferred to the electron. If the energy is sufficient to overcome the energy gap, the electron will enter the conduction band. This is called the photoelectric effect.
Referring once again to
FIG. 2
, the photo energy of the light
46
causes a photoelectric effect in the semiconductor substrate. An electron-hole carrier pair,
50
and
54
, is generated by photoelectric action. A charging action occurs so that the bond pad overlying the substrate
30
exhibits a positive potential with respect to the adjacent bond pad overlying the n-type well
34
. This electrochemical potential difference causes poor electroless plating quality. This is especially true for the ground pad for the integrated circuit device.
In “Designing a Modular Chip-Scale Package Assembly Line,” by T. DiStefano et al, March 1997, the use of a bump pad process is discussed for applications using chip-scale packaging.
Several prior art approaches disclose methods or apparatus for electroless plating. U.S. Pat. No. 4,707,378 to McBride et al discloses a method and an apparatus to control organic contamination levels in an electroless plating bath. A potentiostat is used to measure the contaminant level. An uncovered plating bath is depicted. U.S. Pat. No. 4,699,081 to Mack teaches an apparatus for detecting and adjusting the metal salt concentration in an electroless plating bath. A probe, including a light source and a detector, is placed into the plating tank to monitor the concentration of metal salt based on the light intensity detected. U.S. Pat. No. 5,925,415 to Fry et al discloses a method to electroless plate a metal coating. The metal coating is selectively plated over a monatomic metal layer but not over pendant hydroxy groups. U.S. Pat. No. 4,499,852 to Castner teaches an apparatus for regulating the concentration of dissolved metal in an electroless plating tank. The regulating apparatus comprises a rigid, transparent block with a light source and a light sensor.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective apparatus and very manufacturable method to electroless plate a metal layer in the manufacture of an integrated circuit device.
A further object of the present invention is to provide an apparatus to electroless plate a metal layer onto a semiconductor substrate.
A yet further object is to provide an electroless plating apparatus that prevents light intrusion into the plating tank so that the photoelectric effect is eliminated in the semiconductor substrate.
Another further object of the present invention is to provide a method to electroless plate a metal layer onto a semiconductor substrate.
Another yet further object of the present invention is to provide an electroless plating method where light is shielded from the semiconductor substrate so that the photoelectric effect is eliminated in the semiconductor substrate.
In accordance with the objects of this invention, a new method of electroless plating a metal layer onto a semiconductor substrate in the manufacture of an integrated circuit device has been achieved. A semiconductor substrate is provided. A metal layer is electroless plated onto the semiconductor substrate. Li
Ackerman Stephen B.
Le Thao P.
Megic Corporation
Nelms David
Saile George O.
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