Apparatus, system, and method of dynamic binary translation...

Electrical computers and digital processing systems: processing – Processing control – Arithmetic operation instruction processing

Reexamination Certificate

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C712S244000

Reexamination Certificate

active

11166628

ABSTRACT:
A method may translate a set of source instructions into a set of target instructions, execute the set of target instructions, and unmask a denormal input control bit if the set of source instructions uses a denormal input handling mechanism. A method may detect at least one denormal exception of a faulty target instruction by executing the set of target instructions; assign a predetermined value to one or more denormal operands of the faulty target instruction; and execute the faulty target instruction with the predetermined value for the one or more denormal operands. An apparatus, system, and machine-readable medium may perform such methods.

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patent: 6247117 (2001-06-01), Juffa
patent: 6681322 (2004-01-01), Safford et al.
patent: 2003/0126419 (2003-07-01), Gao et al.
patent: 2004/0015627 (2004-01-01), Desoli et al.
patent: WO 01/27873 (2001-04-01), None
International Search Report. International Application No. PCT/US2006/025321. Mailing date Oct. 25, 2006.

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